DLL Reset Hold Circuit for Stable Power-On Clock Alignment
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Solution Overview
Problem
Semiconductor integrated circuit devices with DLL circuits face instability during power-on sequences due to insufficient power levels and noise interference, leading to malfunction as operating frequencies increase, causing misalignment of clock signals and potential system failures.
Innovation Solution
Incorporating a voltage comparator circuit to hold the reset signal until the power supply voltage stabilizes and a judging circuit to re-issue a reset when counter value differences exceed a threshold, ensuring reliable lock-up operations amidst power fluctuations and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the DLL circuit performs lock-up operation immediately after power-on, then the system can start operating quickly, but the circuit may malfunction due to insufficient power levels and noise interference
Solution Approach 1:
The patent applies preliminary action by detecting the power supply voltage before the DLL circuit performs lock-up operation. The voltage detection circuit measures the power level in advance, and only when the voltage exceeds a predetermined threshold does the system permit the DLL circuit to start its lock-up sequence. This prevents malfunction caused by insufficient power levels during critical startup operations.
Solution Approach 2:
The patent implements feedback through a voltage detection circuit that continuously monitors the power supply voltage and provides feedback signals to control whether the DLL circuit can perform lock-up operations. When the voltage drops below the threshold during operation, the system automatically issues a reset signal to the DLL circuit, ensuring reliable operation by preventing lock-up attempts during low-power conditions.
2Productivity
If the DLL circuit operates at high frequencies, then the system performance improves, but the circuit becomes more susceptible to noise and power fluctuations
Solution Approach 1:
The patent applies preliminary action by performing voltage detection before allowing the DLL circuit to operate. The system checks whether the power supply voltage meets the required threshold before initiating high-frequency operations, ensuring that the circuit has sufficient power margin to withstand noise and voltage fluctuations at higher operating frequencies.
Solution Approach 2:
The patent implements continuous feedback monitoring of the power supply voltage. When the voltage drops below the predetermined threshold during high-frequency operation, the system automatically generates a reset signal to the DLL circuit, preventing noise-induced malfunctions and ensuring stable operation even at high frequencies.
Data Source
AI summary
DLL circuit operating more stably at reset. Voltage comparator circuit 21 outputs comparison result signal to hold circuit 22 at first level when power supply voltage VAA is not higher than reference voltage REF and at second level when power supply voltage VAA exceeds reference voltage REF. Hold circuit 22 outputs reset signal RST that it has received to DLL circuit 23 as it is when comparison result signal indicates first level and at second level, hold circuit 22 holds reset signal RST until comparison result signal becomes first level and then outputs it to DLL circuit 23.