Semiconductor Memory DLL Reset Signal Stability
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Solution Overview
Problem
Semiconductor memory devices face challenges in stably generating reset signals for delay locked loop (DLL) circuits, especially as clock frequencies increase, leading to instability in resetting the DLL circuit.
Innovation Solution
A semiconductor memory device is designed with a pulse signal generator to create normal and extended register control signals, a reset signal generator that receives operating information from the DLL circuit to generate a reset signal, and a DLL circuit that performs a reset operation in response to the generated signal, ensuring stable reset operations even at higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to improve data input/output speed, then the productivity is improved, but the stability of reset signal generation deteriorates
Solution Approach 1:
The patent introduces a reset signal generator as an intermediary component between the clock signal source and the DLL circuit. This generator specifically processes the clock signal to produce a stable reset signal that is less susceptible to frequency-related instability, thereby enabling high-speed operation while maintaining reliable reset functionality.
Solution Approach 2:
The patent changes the parameters of the reset signal generation process by using a dedicated reset signal generator that can adjust its operation based on clock frequency. This allows the system to maintain stable reset signal characteristics across different operating frequencies, resolving the contradiction between high productivity and reliable reset signal generation.
2Productivity
If the clock frequency is increased to improve data input/output speed, then the productivity is improved, but the difficulty of detecting and measuring reset signal stability increases
Solution Approach 1:
The reset signal generator serves as a specialized intermediary that simplifies the detection and measurement of reset signal stability. By dedicating this function to a specific component, the patent makes it easier to monitor and verify reset signal characteristics even at high clock frequencies, reducing the overall difficulty of detecting and measuring system stability.
3Device complexity
If a simple pulse signal method is used to generate reset signal, then the device complexity is reduced, but the reliability of DLL circuit reset deteriorates at high frequencies
Solution Approach 1:
Instead of using a simple pulse signal method, the patent introduces a reset signal generator as an intermediary component. This adds some device complexity but significantly improves the reliability of DLL circuit reset at high frequencies by providing a dedicated mechanism for generating stable reset signals under various operating conditions.
Solution Approach 2:
The reset signal generator is designed to automatically adjust its operation based on the clock signal characteristics, making the system self-regulating. This self-service capability maintains reliable reset functionality without requiring complex external control mechanisms, balancing device complexity with reliability.
Data Source
AI summary
A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal.