Delay Locked Loop Reset Control for Delay Limit Stuck States
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Solution Overview
Problem
Existing delay locked loops in semiconductor memory devices face challenges in resetting the delay locked state due to environmental variations, such as unstable power supply voltage and distorted input clocks, leading to difficulties in adjusting delay amounts beyond maximum or minimum limits, which results in a stuck state and increased power consumption.
Innovation Solution
A semiconductor memory device with a delay locked loop that includes a phase comparison unit, first and second delay circuits, and a control unit for selectively resetting the delay circuits based on delay state signals, allowing for correction of phase differences and indication of required delay amounts beyond maximum or minimum limits, enabling whole or partial resetting of the loop to maintain a stable delay locked state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay locked loop operates without resetting capability, then the delay locked state can be maintained under stable conditions, but the system becomes stuck when environmental variations occur and cannot adapt
Solution Approach 1:
The patent implements a feedback mechanism where delay state signals from the delay circuits are continuously monitored and fed back to the control unit. When the delay amount reaches maximum or minimum limits, the feedback signal triggers an automatic reset of the delay locked loop, enabling the system to adapt to environmental variations such as power supply voltage changes and temperature fluctuations without manual intervention.
Solution Approach 2:
The delay locked loop performs self-resetting through the control unit that automatically detects when delay circuits reach their operational limits and initiates the reset sequence. This self-service mechanism eliminates the need for external control or manual intervention, allowing the system to autonomously recover from stuck states caused by environmental variations.
2Reliability
If the delay locked loop continuously operates without resetting, then continuous signal generation is maintained, but power consumption increases when the system is stuck beyond delay limits
Solution Approach 1:
The patent implements periodic resetting of the delay locked loop based on delay state feedback. Instead of continuous operation without interruption, the system periodically resets the delay circuits when they reach maximum or minimum delay amounts, which prevents the system from remaining in a stuck state and reduces unnecessary power consumption while maintaining continuous signal generation capability.
3Stability of the object's composition
If the delay circuits operate at maximum or minimum delay amounts, then the delay locked state is maintained, but the system cannot adjust further when environmental variations occur
Solution Approach 1:
The patent prepares for future environmental variations by implementing a reset mechanism that activates before the system becomes completely stuck. When delay circuits approach their maximum or minimum limits, the control unit detects this condition and initiates a reset in advance, preventing the system from reaching a completely stuck state and maintaining adaptability to environmental changes.
Data Source
AI summary
A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.