Programmable DLL Retiming for Multi-Stream Data De-Skew
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Solution Overview
Problem
As digital circuitry becomes increasingly complex and transmission speeds increase, data errors due to skew and other transmission effects become more prevalent, leading to inaccurate data reception, and existing de-skew circuitry methods consume high power and increase system size.
Innovation Solution
A de-skew circuitry design that uses a single instance of DLL circuitry to generate configurable delays for multiple data streams, reducing power consumption and system size by serializing data streams and employing a reduced number of voltage-controlled buffers, allowing for precise delay adjustments to minimize errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple voltage-controlled buffers are used to provide configurable delays for multiple data streams, then delay precision and data reception accuracy are improved, but power consumption and system size increase
Solution Approach 1:
The patent merges multiple voltage-controlled buffers into a single shared buffer that serves multiple data streams. The DLL circuitry generates a single delayed clock signal that is distributed to multiple retimer circuits, each handling different data streams. This consolidation maintains the ability to provide configurable delays while significantly reducing the number of voltage-controlled buffers required, thereby lowering power consumption and system size.
Solution Approach 2:
The single voltage-controlled buffer in the DLL circuitry performs a universal function by generating delayed clock signals that are reused across multiple data streams. Instead of having dedicated buffers for each data stream, the same buffer serves all streams by providing a shared delayed clock reference that is distributed to multiple retimer circuits, achieving multi-functionality with minimal hardware.
2Measurement precision
If multiple voltage-controlled buffers are used to provide configurable delays for multiple data streams, then delay precision and data reception accuracy are improved, but system size increases
Solution Approach 1:
The patent merges multiple voltage-controlled buffers into a single shared buffer that serves multiple data streams. The DLL circuitry generates a single delayed clock signal that is distributed to multiple retimer circuits, each handling different data streams. This consolidation maintains the ability to provide configurable delays while significantly reducing the number of voltage-controlled buffers required, thereby lowering power consumption and system size.
Solution Approach 2:
The single voltage-controlled buffer in the DLL circuitry performs a universal function by generating delayed clock signals that are reused across multiple data streams. Instead of having dedicated buffers for each data stream, the same buffer serves all streams by providing a shared delayed clock reference that is distributed to multiple retimer circuits, achieving multi-functionality with minimal hardware.
3Reliability
If de-skew circuitry is placed between transmitter and receiver, then data communication errors are reduced, but circuitry complexity increases
Solution Approach 1:
The de-skew circuitry is segmented into modular retimer circuits that can be independently configured for different data streams. Each retimer circuit is a standardized block that receives data, applies delay based on selected DLL outputs, and forwards the retimed data. This segmentation allows the complex functionality to be distributed across multiple simple, identical modules rather than requiring a single complex circuit, making the overall system more manageable and maintainable.
Solution Approach 2:
The de-skew circuitry employs dynamic delay adjustment through the DLL circuitry that can programmably select from multiple delay values. The delay amount is dynamically configurable based on transmission conditions, allowing the circuit to adapt to different data rates and transmission distances. This dynamic capability is achieved through controlled switches that route clock signals through different numbers of delay stages, providing flexibility without requiring multiple fixed-delay circuits.
Data Source
AI summary
An example system includes a controller having a first controller terminal, a second controller terminal, and a third controller terminal and digitally locked loop (DLL) circuitry having a first DLL terminal and a second DLL terminal, the first DLL terminal coupled to the first controller terminal. The system also includes first retimer circuitry having a first retimer terminal, and a second retimer terminal, and a third retimer terminal, the first retimer terminal coupled to the second DLL terminal and the second retimer terminal coupled to the second controller terminal and second retimer circuitry having a fourth retimer terminal, a fifth retimer terminal, and a sixth retimer terminal, the fourth retimer terminal coupled to the second DLL terminal and the fifth retimer terminal coupled to the third controller terminal.