Delay-Locked Loop Ring Topology for Distortion-Resistant Clock Phasing
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Solution Overview
Problem
Conventional delay locked loops are sensitive to distortion in the input clock signal, leading to unstable and inaccurate generation of delay clock signals, which can result in distorted duty cycles and timing jitter.
Innovation Solution
A delay locked loop design featuring a period locked loop with an even number of delay cells connected in a ring, controlled by selecting signals and a voltage variator to adjust delay times, ensuring the delay clock signals have the same period as the input clock signal and maintaining an exact duty cycle of 50% despite input clock signal distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay locked loop is used to generate delay clock signals, then the basic function of generating multiple clock signals with different phases is achieved, but the generated clock signals become sensitive to input clock signal distortion, leading to unstable duty cycles and timing jitter
Solution Approach 1:
The patent converts the harmful effect of input clock signal distortion into a beneficial feature by using the distortion in a controlled manner. The delay locked loop is designed to intentionally introduce delay that compensates for the distortion, transforming the harmful distortion into a useful mechanism for achieving stable 50% duty cycle output clock signals regardless of input distortion
Solution Approach 2:
The patent changes the delay parameter of the delay locked loop to optimize performance. By adjusting the delay time to be equal to or greater than the distortion amount, the system transforms variable input conditions into stable output characteristics, maintaining consistent duty cycle and timing despite variations in input clock signal
2Manufacturing precision
If delay locked loop adjusts delay time to compensate for input clock distortion, then duty cycle stability is improved, but the complexity of the circuit increases due to additional control mechanisms
Solution Approach 1:
The delay locked loop operates autonomously to detect and compensate for input clock signal distortion without requiring external intervention. The circuit self-adjusts its delay parameter based on the detected distortion level, maintaining stable 50% duty cycle output automatically, which simplifies the overall system architecture despite the internal complexity of the compensation mechanism
3Adaptability or versatility
If conventional delay locked loop is used, then the system can generate multiple phase-shifted clock signals, but timing jitter occurs due to sensitivity to input signal variations
Solution Approach 1:
The patent changes the delay parameter dynamically to compensate for input clock signal variations. By adjusting the delay time based on detected distortion, the system maintains stable timing characteristics across multiple phase-shifted clock signals, eliminating timing jitter while preserving the ability to generate multiple phases
Solution Approach 2:
The delay locked loop incorporates feedback mechanisms to detect timing variations and adjust delay parameters accordingly. This feedback control ensures that timing jitter is minimized while maintaining the generation of multiple phase-shifted clock signals with consistent timing relationships
Data Source
AI summary
A delay locked loop may include a period locked loop portion. The period locked loop portion may include a delay. The delay may include an even number of delay cells dependently connected in the form of a ring configured to generate an even number of delay clock signals. Transition of at least one delay clock signal of the even number of delay clock signals is configured to be controlled in response to an activated one first selecting signal of an even number of first selecting signals, and transition of the remaining clock signals is configured to occur in response to the at least one delay clock signal.