DLL Sampling Circuit with Voltage-Tuned Delay Control
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Solution Overview
Problem
Existing clock delay technologies, such as delay lock loops, face challenges in improving delay ability without increasing circuit area, often requiring additional delay elements which can lead to phase shifts and errors in memory systems due to temperature and voltage changes.
Innovation Solution
A sampling circuit module and memory control circuit unit that incorporate a delay lock loop with a clock control circuit, clock delay circuit, and voltage control circuit, where the driving voltage is adjusted based on a selecting signal to enhance delay ability without adding delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of delay elements in the delay lock loop is increased to improve delay ability, then the delay ability is improved, but the circuit area is increased
Solution Approach 1:
The patent changes the operating voltage parameter of the delay lock loop circuit to improve delay ability. By adjusting the voltage supplied to the DLL circuit, the delay performance is enhanced without adding more delay elements, thus avoiding increase in circuit area. This parameter change approach directly resolves the contradiction between improving delay ability and maintaining compact circuit area.
2Speed
If additional delay elements are added to improve delay ability, then the delay ability is improved, but phase shifts and errors occur due to temperature and voltage changes
Solution Approach 1:
The patent adjusts the operating voltage parameter of the delay lock loop to improve delay performance. By optimizing the voltage supply to the DLL circuit, the system achieves better delay ability while maintaining phase stability and reducing sensitivity to temperature and voltage variations, thereby improving reliability without adding vulnerable delay elements.
Solution Approach 2:
The patent implements a feedback mechanism where the delay lock loop continuously monitors and adjusts its operation to maintain synchronization. This feedback approach compensates for phase shifts caused by temperature and voltage changes, ensuring stable performance without requiring additional delay elements that would increase circuit complexity and vulnerability.
Data Source
AI summary
A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.