Delay-Locked Loop Calibration Using Sequential Delay Codes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loop (DLL) circuits face challenges in maintaining accurate phase alignment due to limitations in the range of acceptable control voltages, leading to incorrect phase locking when the control voltage exceeds safe limits.
Innovation Solution
The proposed DLL circuit incorporates a voltage-controlled delay line (VCDL) calibrated to maintain the control voltage within a safe range by sequentially applying candidate delay codes until the last output signal is 2Π radians out of phase with the first output signal, ensuring correct phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the control voltage range is expanded to accommodate PVT variations, then the adaptability improves, but the risk of incorrect phase locking increases when voltage exceeds safe limits
Solution Approach 1:
The patent applies preliminary calibration action by sequentially testing candidate delay codes before final operation. The calibration mode pre-determines the optimal delay code by evaluating phase differences at multiple candidate codes, storing the result for later use in active mode. This preliminary action ensures the selected code maintains accurate 2Π phase alignment across PVT variations without risking voltage exceedance during normal operation.
Solution Approach 2:
The patent changes the delay code parameter to compensate for PVT variations. By selecting from multiple candidate delay codes (0 to 2^N-1), the system adjusts the delay line's time delay characteristic to maintain accurate phase alignment. The calibration process identifies which parameter value (delay code) achieves the desired 2Π phase difference between first and last output signals under current conditions.
2Measurement precision
If a calibration mode is added to determine optimal delay codes, then the phase alignment accuracy improves, but the device complexity increases
Solution Approach 1:
The patent makes existing circuit components multi-functional to avoid increasing overall device complexity. The phase detector circuit serves dual purposes: during calibration mode, it measures phase differences between first and last output signals to determine optimal delay codes; during active mode, it maintains phase alignment using the pre-determined code. The charge pump and delay line are also used in both calibration and active modes, eliminating the need for separate dedicated calibration hardware.
3Manufacturing precision
If the delay code setter sequentially applies multiple candidate delay codes during calibration, then the manufacturing precision of phase alignment improves, but the time required for initialization increases
Solution Approach 1:
The patent applies partial action by testing candidate delay codes sequentially rather than simultaneously. The delay code setter applies candidate codes in sequence (0, 1, 2, ..., 2^N-1) until the optimal code achieving 2Π phase alignment is found. This partial approach through sequential evaluation reduces the instantaneous complexity and power consumption compared to testing all codes at once, while still ensuring precise phase alignment is achieved.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A delay locked loop circuit comprising: a voltage-controlled delay line (VCDL); a phase detector circuit that is configured to process a first and a last output signal of the VCDL in order to provide: i) an up-pulse signal; and ii) a down-phase signal; a charge pump that is configured to provide a feedback voltage signal based on the up-pulse signal and the down-pulse signal; a phase signal processor that is configured to process the up-pulse signal and the down-pulse signal in order to provide a delay code locking signal, which is representative of whether or not the first output signal is 2 Π radians out of phase with the last output signal; a delay code setter that is configured to provide a delay code setting signal that represents one of a sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration mode of operation: a fixed voltage source provides a fixed voltage signal as a control-voltage signal for the voltage-controlled delay line; while the delay code locking signal represents the first output signal not being 2 Π radians out of phase with the last output signal: the delay code setter applies the delay code setting signal to the VCDL such that it sequentially applies different candidate delay codes to the voltage-controlled delay line until a selected-delay-code is assigned; and when the delay locked loop circuit is in the active mode of operation: a charge pump provides a feedback voltage signal as the control-voltage signal for the voltage-controlled delay line; and the VCDL uses the selected-delay-code as the delay code.