DLL Clock Circuit with Shared Delay Line for Duty Cycle Correction
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Solution Overview
Problem
Conventional semiconductor ICs face challenges in maintaining a stable duty ratio of internal clock signals due to numerous delay elements, leading to increased area occupancy by DLL circuits, which is a concern as semiconductor ICs integrate further.
Innovation Solution
The proposed DLL circuit employs a first feedback loop for duty cycle correction and a second feedback loop for phase detection, using sub delay lines to generate correction and output clock signals, thereby reducing the area occupied by the circuit through efficient delay line configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual loop type DLL circuit is used for duty cycle correction, then the duty ratio stability is improved, but the area occupancy increases due to two delay lines
Solution Approach 1:
The patent merges the duty cycle correction function and delay locking function into a single delay line structure. The first delay line performs both duty cycle correction by adjusting delay of the reference clock signal and delay locking by adjusting delay of the output clock signal, eliminating the need for separate delay lines and reducing overall area occupancy while maintaining dual-loop functionality
Solution Approach 2:
The first delay line is designed to perform multiple functions: it serves as both the duty cycle correction delay line and the delay locking delay line. By making this single component universal, the circuit achieves the performance of a dual-loop DLL circuit without requiring two separate delay lines, thus resolving the contradiction between reliability and area occupancy
Data Source
AI summary
A delay locked loop (DLL) circuit includes a first feedback loop configured to delay a reference clock signal with a delay line, wherein the first feedback loop is further configured to generate a correction clock signal by correcting a duty cycle of the reference clock signal by adjusting a delay of the delay line; and a second feedback loop configured to generate an output clock signal by detecting a phase of the reference clock signal and delaying the correction clock signal with a delay according to the detection result.