Delay-Locked Loop Sleep-Mode Clocking for Low Phase Error

Solution Overview

Problem

Delay-locked loop circuits face challenges in power-saving during idle modes due to increased response time requirements and potential errors from internal leakage when completely powered down.

Innovation Solution

Implementing a dual-mode operation where the circuit operates in both performance and sleep modes, with a reduced frequency during sleep mode to minimize power consumption and maintain low phase errors by externally introducing a phase delay between reference and main clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the delay-locked loop circuit is completely powered down during sleep mode, then power consumption is reduced, but response time increases and phase errors occur due to internal leakage

Engineering Contradiction:

Improvepower consumptionVSAvoidresponse time

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent applies dynamics by making the operating frequency of the delay-locked loop circuit adjustable between two states: a first frequency during performance mode and a second (lower) frequency during sleep mode. This dynamic frequency adjustment allows the circuit to reduce power consumption during idle periods while maintaining the capability to quickly switch back to full performance mode when needed, thus resolving the contradiction between power saving and response time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operating parameter (frequency) of the delay-locked loop circuit based on operational mode. By switching between a first frequency (performance mode) and a second lower frequency (sleep mode), the circuit achieves reduced power consumption during sleep while avoiding complete shutdown. This parameter change enables the circuit to maintain operational readiness with lower power draw, addressing both power consumption and response time requirements.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If the delay-locked loop circuit is completely powered down during sleep mode, then power consumption is reduced, but phase errors increase due to internal leakage

Engineering Contradiction:

Improvepower consumptionVSAvoidphase error

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies dynamics by making the operating frequency of the delay-locked loop circuit adjustable between two states: a first frequency during performance mode and a second (lower) frequency during sleep mode. This dynamic frequency adjustment allows the circuit to reduce power consumption during idle periods while maintaining the capability to quickly switch back to full performance mode when needed, thus resolving the contradiction between power saving and response time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operating parameter (frequency) of the delay-locked loop circuit based on operational mode. By switching between a first frequency (performance mode) and a second lower frequency (sleep mode), the circuit achieves reduced power consumption during sleep while avoiding complete shutdown. This parameter change enables the circuit to maintain operational readiness with lower power draw, addressing both power consumption and response time requirements.

Inventive Principle:

Principle #35Parameter changes

3Speed

If the delay-locked loop circuit operates at full frequency during sleep mode, then response time is maintained, but power consumption increases

Engineering Contradiction:

Improveresponse timeVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the operating frequency of the delay-locked loop circuit adjustable between two states: a first frequency during performance mode and a second (lower) frequency during sleep mode. This dynamic frequency adjustment allows the circuit to reduce power consumption during idle periods while maintaining the capability to quickly switch back to full performance mode when needed, thus resolving the contradiction between power saving and response time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operating parameter (frequency) of the delay-locked loop circuit based on operational mode. By switching between a first frequency (performance mode) and a second lower frequency (sleep mode), the circuit achieves reduced power consumption during sleep while avoiding complete shutdown. This parameter change enables the circuit to maintain operational readiness with lower power draw, addressing both power consumption and response time requirements.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9571080B2Delay-locked loop arrangement and method for operating a delay-locked loop circuit

Publication Date: 2017.02.14 SYNOPSYS INC

AI summary

Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal.