Delay-Locked Loop Sleep Mode for Low-Power Fast Wake-Up
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Solution Overview
Problem
Existing delay-locked loop circuits face challenges in reducing power consumption while maintaining a short response time, as complete power-down leads to increased errors due to leakage and longer recovery times.
Innovation Solution
Implementing a dual-mode operation for the delay-locked loop, where the circuit operates in a performance mode and a sleep mode, with a lower frequency during sleep mode to minimize power consumption and phase errors, using a steering unit to manage the reference and main clock signals and their phase delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the delay-locked loop circuit is completely powered down to save power, then power consumption is reduced, but response time increases and leakage errors accumulate
Solution Approach 1:
The patent applies dynamics by implementing two distinct operational modes (performance mode and sleep mode) that allow the delay-locked loop circuit to adapt its operating characteristics based on system requirements. The circuit dynamically switches between these modes, adjusting its power consumption and response characteristics accordingly, rather than being static in a single operating state.
Solution Approach 2:
The patent applies partial action by implementing a sleep mode where the delay-locked loop circuit operates with reduced functionality (lower frequency) rather than complete power-down. This partial operation maintains essential circuit functionality and reduces leakage errors while still achieving significant power savings, avoiding the extreme of complete shutdown.
2Use of energy by moving object
If the delay-locked loop circuit is completely powered down to save power, then power consumption is reduced, but leakage errors increase over time
Solution Approach 1:
The patent applies dynamics by implementing two distinct operational modes (performance mode and sleep mode) that allow the delay-locked loop circuit to adapt its operating characteristics based on system requirements. The circuit dynamically switches between these modes, adjusting its power consumption and response characteristics accordingly, rather than being static in a single operating state.
Solution Approach 2:
The patent applies partial action by implementing a sleep mode where the delay-locked loop circuit operates with reduced functionality (lower frequency) rather than complete power-down. This partial operation maintains essential circuit functionality and reduces leakage errors while still achieving significant power savings, avoiding the extreme of complete shutdown.
3Reliability
If the delay-locked loop circuit operates at full frequency to maintain accuracy, then phase accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by implementing two distinct operational modes (performance mode and sleep mode) that allow the delay-locked loop circuit to adapt its operating characteristics based on system requirements. The circuit dynamically switches between these modes, adjusting its power consumption and response characteristics accordingly, rather than being static in a single operating state.
Solution Approach 2:
The patent applies parameter changes by modifying the operating frequency parameter based on system state. In performance mode, the circuit operates at full frequency (first frequency) to maintain high phase accuracy. In sleep mode, it transitions to a lower frequency (second frequency) to reduce power consumption, accepting reduced accuracy as a trade-off for energy savings.
Data Source
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Figure 3~4
AI summary
Delay-locked loop arrangement comprising a steering unit (STR) and a delay-locked loop circuit (DLL). The steering unit (STR) is configured to generate a reference clock signal (S_rclk) and a main clock signal (S_mclk) wherein the reference clock signal (S_rclk) and the main clock signal (S_mclk) feature a first frequency during a performance mode of operation. The reference clock signal (S_rclk) and the main clock signal (S_mclk) feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit (DLL) is configured to generate an error signal (S_err) depending on a comparison of the reference clock signal (S_rclk) and a feedback signal (S_fb). Furthermore, the delay-locked loop circuit (DLL) generates the feedback signal (S_fb) depending on the error signal (S_err) and on the main clock signal (S mclk).