DLL Startup Clock Gating for Low-Power Counter Control
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Solution Overview
Problem
Existing DLL circuit designs in semiconductor memory devices, such as DDR-SDRAM, require a constant counter circuit operation during the start-up period, leading to increased power consumption and potential malfunctions due to hazards caused by delayed state transitions during power-down modes.
Innovation Solution
A DLL circuit unit comprising a counter circuit that intermittently operates the DLL circuit by generating a first clock signal and supplying a control signal to inactivate the internal clock during the start-up period, reducing power consumption and preventing hazards by synchronizing clock activation and inactivation with the DLL circuit's state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the counter circuit operates constantly to count the start-up period, then the DLL circuit can be properly controlled during startup, but power consumption increases
Solution Approach 1:
The counter circuit is designed to operate periodically rather than continuously. It activates to count the start-up period when needed, then enters a low-power state. This periodic operation maintains the necessary functionality for DLL startup control while significantly reducing overall power consumption compared to constant operation.
2Use of energy by moving object
If the counter circuit is operated intermittently to save power, then power consumption is reduced, but hazards may occur due to delayed state transitions
Solution Approach 1:
The system performs preliminary actions by activating the counter circuit in advance before the actual start-up period begins. This ensures that the counter is already running and ready to accurately measure the start-up period, preventing hazards related to delayed state transitions while still allowing the counter to be deactivated afterward to save power.
Solution Approach 2:
The counter circuit incorporates feedback mechanisms that monitor the DLL circuit's state transitions. When the DLL circuit transitions states, the feedback signal triggers the counter to activate or deactivate accordingly. This feedback-based control ensures that the counter operates only when necessary, preventing hazards while minimizing power consumption.
3Loss of time
If the DLL circuit is activated during power-down mode, then the start-up period can be measured, but malfunctions may occur due to delayed state transitions
Solution Approach 1:
The counter circuit is activated in advance before the DLL circuit enters the power-down mode. This preliminary activation ensures that the counter is already running and will accurately capture the start-up period measurement. By preparing the counter beforehand, the system avoids malfunctions that could occur if the counter were activated after the power-down mode began, which might delay state transition detection.
Data Source
AI summary
A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.