Delay Locked Loop Step Control for Faster Stable Locking
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Solution Overview
Problem
Conventional digital delay locked loop (DLL) circuits face challenges in achieving initial lock quickly due to complex timing requirements for multiplexer selection, which can lead to glitches in the clock signal.
Innovation Solution
The proposed DLL circuit includes a phase detector, step size controllers, and a delay line with modular delay elements, allowing for adjustable step sizes during lock acquisition, transitioning from coarse to fine adjustments as the lock is achieved, and distributing delay evenly across multiple delay blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide multiplexer with many taps is used to select delay in a conventional digital DLL, then the delay selection capability is improved, but the lock acquisition time increases and clock glitches occur
Solution Approach 1:
The delay line is divided into multiple delay blocks, each containing a subset of taps. Instead of using one wide multiplexer to select from all taps, the patent uses multiple smaller multiplexers, each handling a segment of the delay line. This segmentation allows parallel operation of the multiplexers, significantly reducing the time required to acquire lock while maintaining full delay selection capability.
2Adaptability or versatility
If a wide multiplexer with many taps is used to select delay in a conventional digital DLL, then the delay selection capability is improved, but clock signal stability deteriorates due to glitches
Solution Approach 1:
By segmenting the delay line into multiple blocks with separate multiplexers, each multiplexer handles fewer taps simultaneously. This reduces the complexity and switching activity within each multiplexer, minimizing clock glitches and improving overall clock signal stability while preserving the full range of delay selection capability.
3Measurement precision
If the DLL steps across the inverter chain one tap at a time using a multiplexer, then delay precision is improved, but the timing complexity increases
Solution Approach 1:
The delay line is segmented into multiple blocks, each with its own multiplexer. This allows parallel operation of multiple multiplexers, each independently selecting taps within their respective blocks. The segmentation reduces the timing complexity by distributing the selection logic across multiple simpler units operating in parallel, while maintaining fine delay precision through the combined resolution of all segments.
Solution Approach 2:
The patent implements dynamic step size adjustment where the DLL can take larger steps initially to approach the target delay quickly, then transition to finer steps for precise locking. This dynamic behavior reduces the overall timing complexity by adapting the search granularity to the current locking stage, rather than using a fixed fine-grained approach throughout.
Data Source
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AI summary
A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.