Synchronous Data Reception with DLL-Based Strobe Alignment
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Solution Overview
Problem
Source synchronous systems face misalignment issues due to inaccuracies in clock generation circuits and uneven propagation paths of data strobes and data signals, leading to suboptimal reception conditions in microelectronics.
Innovation Solution
An apparatus and method utilizing a resistor network, composite delay elements, and delay-locked loops (DLLs) to compensate for signal misalignment by generating delayed data bit signals that align with data strobes, ensuring equal propagation paths and optimizing phase alignment on a synchronous data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If data strobes and data signals are routed along equal propagation paths on the system board, then signal alignment is improved, but additional propagation delays within the receiving device cause skewing of the synchronous transmission
Solution Approach 1:
The patent applies preliminary action by introducing composite delay elements that pre-compensate for the additional propagation delays within the receiving device. The delay elements are configured to delay data strobes by specific amounts (e.g., 0.25 to 2.0 nanoseconds) before they reach the synchronous receivers, thereby equalizing the total propagation time of data strobes and data signals through the entire system board and device interface.
Solution Approach 2:
The patent applies local quality by providing different delay amounts to different data strobes based on their specific propagation path characteristics. Each composite delay element can be independently configured with different delay values (0.25ns, 0.5ns, 0.75ns, 1.0ns, 1.25ns, 1.5ns, 1.75ns, or 2.0ns) to match the specific propagation delays of corresponding data signals, thereby achieving precise local signal alignment.
2Productivity
If clock generation circuits are used to gate data signals and switch strobes, then data transmission is enabled, but inaccuracies in clock generation cause misalignment of data strobes and data signals
Solution Approach 1:
The patent applies feedback by using delay-locked loops (DLLs) that receive feedback from the actual propagation delays experienced by data signals. The DLLs automatically adjust the delay amounts of composite delay elements based on this feedback, compensating for variations in clock generation accuracy and ensuring that data strobes and data signals remain aligned despite clock inaccuracies.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay parameters of composite delay elements to compensate for clock generation inaccuracies. The system can change delay amounts from 0.25ns to 2.0ns in incremental steps based on measured propagation delays, thereby adapting to variations in clock accuracy and environmental conditions.
3Ease of operation
If the strobe signal is distributed to all internal synchronous receivers within the receiving device, then data reception is enabled, but the additional propagation lengths add delay and skew the phase of synchronous transmission
Solution Approach 1:
The patent applies preliminary action by introducing composite delay elements at the input of the receiving device that pre-delay data strobes to compensate for the additional propagation lengths required to reach internal synchronous receivers. This preliminary delay ensures that data strobes and data signals arrive at the receivers simultaneously, despite the different path lengths within the device.
Solution Approach 2:
The patent applies segmentation by dividing the receiving device into multiple segments, each with its own composite delay element configured for the specific propagation characteristics of that segment. This allows each receiver to receive compensated signals optimized for its specific location and propagation path length within the device.
Data Source
AI summary
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.