DLL TAP Switching With Clock Stop Timing Control

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Solution Overview

Problem

Conventional DLL circuits are slow in switching the TAP output, requiring time for resetting and restarting, which hampers the speed of output signal switching.

Innovation Solution

A DLL circuit comprising a phase delay circuit, a selection circuit, a detection circuit, and a clock stop circuit, where the clock stop circuit stops the clock signal input to the phase delay circuit for a predetermined period during TAP switching, detected by the detection circuit, to prevent unnecessary edges and enhance switching speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the DLL circuit is reset once and the TAP output is switched, then the switching of output signal is achieved, but it takes time from resetting to restarting the DLL

Engineering Contradiction:

Improveswitching speed of TAP outputVSAvoidtime from resetting to restarting DLL

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The clock stop circuit stops the clock signal input to the phase delay circuit in advance before TAP switching occurs. This preliminary action prevents unnecessary edge generation and allows the selection circuit to switch TAP outputs without requiring a full DLL reset and restart sequence, thereby reducing the time loss associated with resetting and restarting the DLL circuit.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the clock signal continues to be input during TAP switching, then continuous operation is maintained, but unnecessary edges are generated causing signal inversion issues

Engineering Contradiction:

Improvesignal accuracyVSAvoidunnecessary edges causing signal inversion

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The clock stop circuit extracts or removes the clock signal input to the phase delay circuit during the TAP switching period. By taking out the clock signal temporarily, the system prevents the generation of unnecessary edges that would otherwise cause signal inversion issues in the output, thereby improving signal accuracy without requiring complete system shutdown.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If the DLL circuit switches TAP output rapidly, then productivity is improved, but switching accuracy may be compromised

Engineering Contradiction:

Improveswitching speed of output signalVSAvoidswitching accuracy of TAP output

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The detection circuit detects the timing of TAP switching and triggers the clock stop circuit to stop the clock signal in advance before the actual switching occurs. This preliminary action ensures that unnecessary edges are prevented from generating during the switching transition, maintaining switching accuracy even when operating at high speeds for improved productivity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12095468B2DLL circuit and distance measuring sensor

Publication Date: 2024.09.17 SONY SEMICON SOLUTIONS CORP

AI summary

A DLL circuit (110) includes a phase delay circuit (114), a selection circuit (115), a detection circuit (117), and a clock stop circuit (116). The phase delay circuit (114) generates a plurality of delayed signals having different phases according to a clock signal. The selection circuit (115) selects one of the plurality of delayed signals as an output signal according to a setting signal. The detection circuit (117) detects a timing of switching the setting signal. The clock stop circuit (116) stops input of the clock signal to the phase delay circuit (114) for a predetermined period including the timing detected by the detection circuit (117).