Delay-Locked Loop Tap Switching for Faster Clock Synchronization
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing internal clock signals with externally-generated clock signals due to time delays, requiring additional circuits that increase chip size and thermal dissipation.
Innovation Solution
A delay locked loop (DLL) circuit that selects a feedback quantity from a first intermediate location for initial synchronization and then switches to a second location for maintaining synchronization, reducing the need for additional logic and duty cycle correction circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DLL circuits are used to synchronize internal and external clock signals, then phase alignment is achieved, but chip size and thermal dissipation increase due to additional circuits
Solution Approach 1:
The patent extracts and eliminates unnecessary duty cycle correction circuits from the traditional DLL design. By using a simplified delay line with tap points that directly provide the required phase adjustments, the circuit removes the separate duty cycle correction block, thereby reducing chip area while maintaining synchronization reliability
Solution Approach 2:
The delay line elements serve multiple functions simultaneously: they provide phase shifting, delay adjustment, and implicit duty cycle correction. The tap points generate clock signals with different phase relationships while inherently maintaining proper duty cycles, eliminating the need for dedicated duty cycle correction circuits
2Reliability
If traditional DLL circuits are used to synchronize internal and external clock signals, then phase alignment is achieved, but thermal dissipation increases due to additional circuits
Solution Approach 1:
The patent removes unnecessary duty cycle correction circuits from the traditional DLL design. By using a simplified delay line with tap points that directly provide the required phase adjustments, the circuit removes the separate duty cycle correction block, thereby reducing thermal dissipation while maintaining synchronization reliability
Solution Approach 2:
The delay line elements self-adjust to provide proper phase relationships and duty cycles without requiring additional correction circuits. The tap points inherently generate clock signals with appropriate characteristics, making the circuit self-sufficient and reducing overall power consumption and heat generation
3Reliability
If additional logic and duty cycle correction circuits are added to achieve synchronization, then clock signal alignment is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates unnecessary duty cycle correction circuits from the traditional DLL design. By using a simplified delay line with tap points that directly provide the required phase adjustments, the circuit removes the separate duty cycle correction block, thereby reducing device complexity while maintaining synchronization reliability
Solution Approach 2:
The patent merges the phase shifting function and duty cycle correction function into a single delay line structure. The tap points simultaneously provide both phase adjustment and duty cycle maintenance, eliminating the need for separate logic blocks and simplifying the overall circuit architecture
Data Source
AI summary
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop.