DLL Update Control Using Phase-Difference Threshold Counting
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Solution Overview
Problem
Conventional DLL circuits in semiconductor ICs face challenges in accurately controlling the phase of internal clock signals due to irregular variations in phase comparison detection results, leading to ineffective update operations and limited control capabilities.
Innovation Solution
A DLL circuit with an updated control apparatus that generates a valid interval signal and update control signal by determining the difference between the number of first and second logical values in the phase detection signal, allowing the shift register to update the delay value supplied to the delay line, and includes a switching portion, counting portions, and an update control portion to manage these signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional update control apparatus using a low pass filter is used to accumulate phase comparison results, then abnormal operations can be prevented, but the update condition becomes complicated and the update operation becomes ineffective when irregular variations occur
Solution Approach 1:
The invention changes the update condition from a complex multi-cycle accumulation check to a simple threshold-based comparison. By comparing the absolute value of the accumulated phase difference against a predetermined threshold, the system maintains reliability while dramatically simplifying the update condition logic, enabling effective updates even during irregular phase variations.
Solution Approach 2:
The invention applies different processing logic to different aspects of the phase comparison data. The accumulation of phase differences is performed continuously, but the update decision is made locally by simply comparing the accumulated value against a threshold, rather than applying complex global rules across multiple cycles.
2Reliability
If the update control apparatus requires three consecutive phase comparison detection result values to match, then abnormal operations are prevented, but the DLL circuit cannot accurately control the phase when irregular variations occur
Solution Approach 1:
The invention changes the update trigger condition from requiring three consecutive matching values to triggering when the accumulated phase difference exceeds a threshold. This parameter change allows the system to respond to genuine phase errors while filtering out random noise, maintaining reliability while improving phase control accuracy during irregular variations.
Solution Approach 2:
The system performs preliminary accumulation of phase differences over multiple cycles before making an update decision. This preliminary action filters out random variations while preserving genuine phase errors, enabling accurate phase control without requiring strict consecutive matching conditions.
3Productivity
If a simple update condition is used to enable frequent updates, then phase control responsiveness is improved, but abnormal operations may occur due to noise and irregular variations
Solution Approach 1:
The system performs preliminary accumulation of phase difference values over multiple clock cycles before triggering an update. This preliminary action acts as a filter that preserves genuine phase errors while averaging out random noise and irregular variations, enabling frequent yet reliable updates without causing abnormal operations.
Solution Approach 2:
The system uses feedback by continuously monitoring the accumulated phase difference and comparing it against a threshold. This feedback mechanism ensures that updates are triggered only when genuine phase corrections are needed, maintaining operation stability while allowing frequent updates when appropriate.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.