On-Chip Delay Locked Loop Timing Calibration
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Solution Overview
Problem
Integrated circuits in communication systems face challenges in maintaining precise timing delays due to environmental variations such as temperature and aging, especially in harsh environments like space applications, where accurate calibration of timing delays is necessary to ensure reliable operation.
Innovation Solution
The integration of a Delay Locked Loop (DLL) circuit within the integrated circuit, which includes a variable clock, an arbiter circuit, and control logic, allows for the measurement and adjustment of propagation delays by comparing the timing of a reference clock signal to a delayed clock signal, enabling precise calibration and maintaining accurate timing despite environmental changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing delay calibration is performed using external instruments, then measurement accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The integrated circuit performs timing delay calibration autonomously using internal components including a delay element, arbiter circuit, and counter. The circuit generates its own calibration signals and processes measurements without external instrumentation, enabling self-calibration functionality that reduces system complexity while maintaining picosecond-level measurement accuracy
Solution Approach 2:
An on-chip delay element is introduced as an intermediary component to generate controllable delay signals for calibration purposes. This delay element acts as a mediator between the clock signal source and the arbiter circuit, enabling precise timing measurements to be performed using simple internal components rather than complex external equipment
2Measurement precision
If timing delay calibration is performed externally, then manufacturing cost increases, but measurement accuracy is improved
Solution Approach 1:
The calibration functionality is integrated directly into the semiconductor chip during manufacturing, allowing timing delay measurements to be performed and stored in lookup tables without requiring post-manufacturing external calibration equipment. This approach reduces manufacturing costs by eliminating the need for expensive external calibration instruments while achieving picosecond-level measurement accuracy through internal calibration circuits
Solution Approach 2:
Timing delay calibration is performed during the manufacturing process itself, before the product is deployed. The calibration measurements are taken and stored in lookup tables during fabrication, eliminating the need for subsequent external calibration operations. This preliminary calibration action reduces both manufacturing complexity and long-term operational costs
3Device complexity
If fixed timing delay is used in harsh environments, then circuit simplicity is maintained, but timing precision deteriorates due to temperature and aging variations
Solution Approach 1:
The system transitions from fixed timing delay to dynamic, adaptive timing calibration. A variable delay element is used that can adjust its delay characteristics based on environmental conditions such as temperature and aging. The calibration system periodically updates lookup tables with corrected timing values, enabling the circuit to adapt to changing environmental conditions while maintaining timing precision without requiring complex real-time adjustment mechanisms
Solution Approach 2:
Calibration data for different temperature and aging conditions is pre-computed and stored in lookup tables during manufacturing. When the circuit operates in harsh environments, it retrieves pre-calibrated timing values from these tables based on sensed environmental conditions, avoiding the need for complex real-time calibration while maintaining timing precision across varying conditions
Data Source
AI summary
A system and method for measuring or calibrating a delay through a circuit path within an integrated circuit is disclosed. In some embodiments, a delay locked loop (DLL) circuit is provided. An arbiter circuit in the DLL compares timing of a clock signal and a delayed version of the clock signal that has passed through the circuit path. The percentage of the clock signal with feature that arrives before the corresponding feature of the delayed clock can be an indication of the delay timing through the path relative to a period of the clock signal and used as feedback in the DLL.