DLL Clock Buffer Timing Compensation for Precise Delay Locking
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Solution Overview
Problem
Conventional DLL circuits in semiconductor ICs face precision issues in delay locking due to varying toggle timing frequencies of clock signals during duty cycle correction, leading to unreliable clock delay locking operations.
Innovation Solution
A DLL circuit design that includes a clock input buffer for duty cycle correction, a timing compensation unit to adjust toggle timing, and a duty cycle control unit to generate control signals, ensuring precise delay locking by compensating for toggle timing changes and maintaining stable clock signal duty ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle correction is performed by adjusting voltage level in clock input buffer, then duty ratio of reference clock signal is improved, but toggle timing frequency varies causing delay locking precision to deteriorate
Solution Approach 1:
The invention separates the duty cycle correction function from the clock buffering function by introducing a dedicated duty cycle correction unit that operates independently on the clock signal path. This segmentation allows duty cycle adjustment without affecting the toggle timing of the original clock signal, thereby maintaining delay locking precision while achieving accurate duty ratio correction.
Solution Approach 2:
The invention introduces an intermediary duty cycle correction unit that processes the clock signal between the external clock input and the internal clock distribution. This intermediary component corrects the duty cycle by selectively extending or truncating clock pulses based on detected duty ratio deviations, while preserving the original signal's timing characteristics for delay locking operations.
2Speed
If numerous delay elements are included in semiconductor IC for high-speed operation, then operational speed increases, but duty ratio of internal clock signal varies
Solution Approach 1:
The invention implements a feedback mechanism where the duty cycle control unit continuously detects the duty ratio of the reference clock signal and dynamically adjusts the duty cycle correction operation accordingly. This closed-loop feedback system compensates for duty ratio variations introduced by numerous delay elements, maintaining stable duty ratios even in high-speed semiconductor ICs with multiple delay stages.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.