DLL Timing Control for DDR Memory Low-Power Clock Relock
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Solution Overview
Problem
DDR SDRAM devices experience read or write errors when exiting low power consumption mode due to significant power supply voltage changes, causing misalignment of internal and external clocks.
Innovation Solution
A DLL circuitry system with a timer unit that generates a DLL enable signal to relock the internal clock signal with the external clock signal based on predefined timer conditions, ensuring phase alignment even in low power consumption mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit is always active to maintain clock alignment, then clock phase locking is ensured, but power consumption increases
Solution Approach 1:
The timer unit activates the DLL circuit in advance before the memory device exits low power mode, ensuring the DLL circuit is ready to quickly realign clock phases without waiting for voltage stabilization or error occurrence. This preliminary activation prevents data errors while avoiding continuous operation.
Solution Approach 2:
The DLL circuit operates periodically rather than continuously - it is activated only when needed (upon exit from low power mode) and deactivated during low power modes. The timer unit controls this periodic operation by generating enable signals based on timing conditions, reducing overall power consumption while maintaining reliability when required.
2Use of energy by moving object
If the DLL circuit is deactivated in low power mode to reduce power consumption, then power savings are achieved, but clock alignment is lost causing read/write errors
Solution Approach 1:
The timer unit activates the DLL circuit in advance before the memory device exits low power mode, ensuring the DLL circuit is ready to quickly realign clock phases without waiting for voltage stabilization or error occurrence. This preliminary activation prevents data errors while avoiding continuous operation.
Solution Approach 2:
The timer unit monitors the power supply voltage stabilization condition and uses this feedback to determine when to activate the DLL circuit. By detecting when voltage has stabilized after exiting low power mode, the timer ensures the DLL circuit is activated at the optimal moment to prevent alignment errors.
3Loss of time
If the DLL circuit is activated immediately upon exiting low power mode, then clock realignment is attempted quickly, but read/write errors occur due to voltage instability
Solution Approach 1:
The timer unit monitors the power supply voltage stabilization condition and uses this feedback to determine when to activate the DLL circuit. By detecting when voltage has stabilized after exiting low power mode, the timer ensures the DLL circuit is activated at the optimal moment to prevent alignment errors.
Solution Approach 2:
The timer unit activates the DLL circuit in advance before the memory device exits low power mode, ensuring the DLL circuit is ready to quickly realign clock phases without waiting for voltage stabilization or error occurrence. This preliminary activation prevents data errors while avoiding continuous operation.
Data Source
AI summary
Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.