Delay Locked Loop Timing Pulses for Variable Clock Frequencies
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Solution Overview
Problem
Conventional delay locked loop (DLL) circuits malfunction when there is a significant change in the frequency of the source clock, due to predetermined timing pulses that do not synchronize with the actual delay of the internal clock path, limiting the applicable frequency bandwidth and leading to increased operation time.
Innovation Solution
A DLL circuit with a timing pulse generating unit that adjusts the number of timing pulses based on the source clock frequency, allowing for optimal delay shifting update periods and synchronization with the source clock frequency, regardless of changes in frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If predetermined timing pulses are used for delay shifting update periods, then the DLL circuit structure is simple, but the circuit malfunctions when there is a significant change in source clock frequency
Solution Approach 1:
The timing pulse generating unit dynamically adjusts the number of timing pulses based on the detected source clock frequency. When the source clock frequency increases, more timing pulses are generated to maintain proper synchronization, and vice versa. This dynamic adaptation resolves the contradiction by making the DLL circuit frequency-dependent rather than fixed, ensuring reliable operation across varying frequencies without significantly increasing structural complexity.
Solution Approach 2:
The patent changes the parameter of timing pulse quantity based on source clock frequency. The timing pulse generating unit detects the source clock frequency and adjusts the number of timing pulses accordingly. This parameter change allows the DLL circuit to adapt to frequency variations, maintaining reliable operation while keeping the overall circuit structure relatively simple.
2Ease of manufacture
If a fixed number of timing pulses is used, then the circuit design is straightforward, but the applicable frequency bandwidth is limited
Solution Approach 1:
The timing pulse generating unit implements dynamic pulse generation where the number of timing pulses varies with source clock frequency. This dynamic approach expands the applicable frequency bandwidth while maintaining relatively straightforward circuit design through the use of a frequency detection mechanism and conditional pulse generation logic.
Solution Approach 2:
The timing pulse generating unit serves multiple functions: it generates timing pulses for delay shifting, detects source clock frequency, and adjusts pulse quantity based on detected frequency. This multi-functionality expands the DLL circuit's adaptability to various frequencies while keeping the overall design integrated and relatively simple.
3Device complexity
If predetermined timing pulses are used, then the initial circuit setup is simple, but the operation time increases when frequency changes occur
Solution Approach 1:
The timing pulse generating unit incorporates feedback by detecting the source clock frequency and using this information to adjust the number of timing pulses. This feedback mechanism enables the DLL circuit to quickly adapt to frequency changes, reducing operation time compared to fixed pulse schemes that would require longer stabilization periods when frequency variations occur.
Solution Approach 2:
The dynamic adjustment of timing pulse quantity based on real-time frequency detection allows the DLL circuit to optimize its operation time for each frequency condition. When frequency changes occur, the circuit immediately adapts by generating an appropriate number of timing pulses, avoiding the extended operation times that would result from fixed pulse schemes.
Data Source
AI summary
A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.