Delay-Locked Loop Timing Control for Variable Clock Cycles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay-locked loop (DLL) devices face challenges in adjusting input clocks with varying cycles, often resulting in insufficient or excessive delay due to over shift issues, particularly when the input clock cycle is small or large.
Innovation Solution
A DLL device comprising a delay line, replica circuit, phase detector, and delay controller, where the cycle of the control clock is adjusted to be larger than the replica delay time length, allowing the generation and adjustment of a delay code to synchronize the input clock within a preset cycle, applicable to any input clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the DLL uses a conventional delay adjustment mechanism, then it can adjust the delay clock for standard input clock cycles, but it cannot properly handle input clocks with small or large cycles due to over shift issues
Solution Approach 1:
The patent implements dynamic control of the delay code generation timing by adjusting the cycle of the control clock. The delay controller dynamically modifies the control clock cycle to be larger than the replica delay time length, enabling the delay code to be generated at appropriate time points that adapt to different input clock cycles. This dynamic adjustment resolves the contradiction by making the DLL adaptable to various input clock cycles while maintaining reliable delay accuracy through proper timing control.
2Manufacturing precision
If the DLL adjusts delay for small input clock cycles, then it may achieve sufficient delay, but over shift issues cause insufficient or excessive delay
Solution Approach 1:
The patent employs a feedback mechanism where the phase detector compares the input clock with the feedback clock and generates a delay control signal that is fed back to the delay controller. This closed-loop feedback system allows the DLL to automatically adjust the delay code timing based on the actual phase difference, ensuring precise delay control for small input clock cycles while maintaining operational stability by preventing over shift through continuous monitoring and correction.
3Reliability
If the DLL is designed for large input clock cycles, then over shift issues are improved, but the DLL cannot adjust the delay clock within the preset cycle
Solution Approach 1:
The patent implements preliminary action by pre-adjusting the control clock cycle to be larger than the replica delay time length before delay code generation. This preliminary timing adjustment ensures that the delay code is generated at the correct time point, allowing the DLL to maintain reliable delay control for large input clock cycles while still achieving timely delay adjustment within the preset cycle by preparing the control timing in advance.
Data Source
AI summary
A DLL device and an operation method for the DLL device are provided. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays an input clock in response to a delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delayed clock. The phase detector compares the input clock with the feedback clock to generate a delay control signal. The delay controller generates the delay code at a first time point according to the delay control signal based on a control clock and delays a replica delay time length to provide the delay code to the delay line at a second time point. The delay line adjusts the input clock at the second time point. A cycle of the control clock is adjusted to be larger than the replica delay time length.