DLL Clock Update Interval Control for Fast Stable Locking
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Solution Overview
Problem
High-frequency clock signals often make it difficult for DLL circuits in semiconductor devices to reach the lock state within the maximum lock cycle, leading to increased lock cycles and control jitter due to overshoot phenomena when the update signal generation interval is either too long or too short.
Innovation Solution
A semiconductor device with a DLL circuit that includes a variable update signal generation interval, allowing the DLL circuit to be quickly shifted to a lock state by adjusting the frequency division ratio of the update signal based on actual measurements of delay and control delays, preventing overshoot and reducing lock cycle duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a constant generation interval of the update signal is used, then the DLL circuit operation is simple, but the lock cycle becomes excessively long when using high-frequency clock signals
Solution Approach 1:
The update control circuit dynamically changes the generation interval of the update signal based on the operational state of the DLL circuit. Initially, the update signal is generated at a first interval to quickly adjust the phase, and after detecting a lock state, it switches to a second interval to maintain stability. This dynamic adjustment resolves the contradiction by adapting the update frequency to the current operational phase.
Solution Approach 2:
The update control circuit employs periodic action with varying periods. The update signal is generated periodically at different intervals depending on whether the DLL is in acquisition or lock state. This periodic variation allows rapid initial locking followed by stable maintenance, addressing both the speed and simplicity requirements.
2Loss of time
If the generation interval of the update signal is made short to reduce lock cycle, then the lock cycle decreases, but overshoot phenomena occur causing control jitter
Solution Approach 1:
The system dynamically adjusts the update signal interval based on the DLL's operational state. During acquisition, a shorter first interval enables rapid locking. After detecting lock state through phase comparison, the system transitions to a longer second interval to prevent overshoot and maintain stability. This dynamic adaptation resolves the contradiction between fast locking and stable control.
Solution Approach 2:
The update control circuit uses feedback from the phase determination circuit to adjust the update signal generation interval. When the phase difference indicates lock state, the feedback mechanism triggers a switch from the first interval to the second interval, preventing overshoot while maintaining rapid response capability during acquisition.
3Stability of the object's composition
If the generation interval of the update signal is made long to prevent overshoot, then control stability improves, but the lock cycle becomes excessively long
Solution Approach 1:
The update control circuit implements dynamic interval adjustment, using a short first interval during acquisition to minimize lock cycle duration, and switching to a long second interval after lock detection to ensure stability. This temporal differentiation resolves the contradiction by applying appropriate intervals at appropriate times.
Solution Approach 2:
The system performs preliminary action with a short update interval during the acquisition phase to quickly establish lock, then transitions to a longer interval for maintenance. This preliminary rapid adjustment followed by stable maintenance resolves the contradiction between speed and stability.
Data Source
AI summary
Disclosed herein is a device includes a first delay circuit delaying a first clock signal according to a count value to generate a second clock signal, a phase determination circuit comparing a phase of the first clock signal with a phase of the second clock signal to generate a phase determination signal, an up-down counter updating the count value according to the phase determination signal each time an update signal is activated, and an update control circuit generating the update signal at a variable interval.