DLL Update Control for Low-Power Semiconductor Clock Phase Locking
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Solution Overview
Problem
Conventional DLL circuits in semiconductor integrated circuits continue to consume power even in situations similar to power down mode due to continuous updates, despite their ability to reduce power consumption during actual power down modes, leading to inefficiencies in power management.
Innovation Solution
A semiconductor integrated circuit with an update control unit that generates an update control signal based on the frequency of read operations, enabling or disabling the DLL circuit's update operation to distinguish between actual and pseudo power down modes, thereby reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DLL circuit continuously performs updates to maintain clock phase accuracy, then the reliability of clock signal is improved, but the power consumption increases even in low-activity periods
Solution Approach 1:
The DLL circuit's update operation is made dynamic by introducing an update control signal that adjusts the circuit's activity state based on system conditions. The update control unit monitors system state and dynamically switches the DLL between continuous update mode and stopped mode, allowing the circuit to adapt its power consumption to actual operational needs while maintaining reliability when required.
Solution Approach 2:
The invention changes the operational parameter of the DLL circuit from a fixed continuous update state to a variable state controlled by the update control signal. By modifying the update frequency parameter based on system activity (stopping updates during power down mode and low read operation frequency), the circuit achieves optimal balance between clock phase accuracy and power consumption.
2Use of energy by moving object
If the DLL circuit stops operation during power down mode to reduce power consumption, then the power efficiency is improved, but the clock phase may drift when the circuit resumes operation
Solution Approach 1:
The update control unit implements a feedback mechanism by monitoring system state (power down mode status and read operation frequency) and using this information to control the DLL update operation. This feedback loop ensures that the DLL stops updating only when appropriate (reducing power consumption) and resumes updates when needed (maintaining clock phase stability), thus resolving the contradiction between power efficiency and phase stability.
3Adaptability or versatility
If the DLL circuit distinguishes between power down mode and pseudo power down mode based on read operation frequency, then the power management precision is improved, but the control complexity increases
Solution Approach 1:
Rather than implementing a complex multi-parameter analysis system, the invention uses a simplified approach by monitoring only the read operation frequency parameter. This partial action principle allows the update control unit to distinguish between power down mode and pseudo power down mode using a single measurable parameter, achieving adequate power management precision without excessive control complexity.
Data Source
AI summary
A semiconductor integrated circuit includes an update control unit configured to generate an update control signal in response to a first command and a second command; and a DLL (Delay Locked Loop) circuit configured to generate an output clock by controlling a phase of an external clock in response to the update control signal.