DLL Update Control for Jitter-Stable Phase Alignment
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Solution Overview
Problem
High-frequency clock signals in semiconductor ICs lead to short periods for reference and feedback clock signals, causing errors in phase detection due to jitter components, which degrades the performance and reliability of DLL circuits.
Innovation Solution
A semiconductor IC with a DLL controlling block that enables or disables an update enable signal based on voltage level changes in the phase detecting signal, and includes a delay locked loop to control the frequency of the delay amount in the reference clock signal, using an operation controlling unit, shifting unit, phase state discriminating unit, and delay controlling unit to manage phase differences and jitter effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency clock signals are used to achieve high speed operation, then operation speed is improved, but phase detection accuracy deteriorates due to jitter components and short periods
Solution Approach 1:
The patent applies preliminary action by detecting voltage level changes of the phase detecting signal over a predetermined time period before making phase comparison decisions. The DLL controlling block monitors the phase detecting signal and only responds when a sustained voltage level change is detected, filtering out transient jitter-induced variations. This preliminary detection and filtering action prevents jitter from causing erroneous phase comparisons while maintaining high-frequency operation.
2Reliability
If the DLL circuit continuously updates the delay amount to maintain phase alignment, then phase synchronization is improved, but power consumption increases due to unnecessary current consumption
Solution Approach 1:
The patent implements periodic action by enabling the update enable signal only when a voltage level change of the phase detecting signal is detected during a predetermined time period. Instead of continuous updating, the DLL circuit periodically adjusts the delay amount based on actual phase detection events. This periodic update mechanism maintains phase synchronization reliability while minimizing unnecessary current consumption during stable operating conditions.
Data Source
AI summary
A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.