Delay-Locked Loop Update Timing for Lower Memory Power
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Solution Overview
Problem
Existing delay locked loop devices in memory systems consume high power when updating delay codes in response to temperature changes, as they typically require updates at any time, leading to increased energy usage.
Innovation Solution
A delay locked loop device with an update circuit that includes a flag generating circuit and an enable circuit, which provides an update flag based on a default time interval shorter than the memory device's refresh cycle, enabling the delay locked loop only within this interval to transition the enable signal from a first to a second logic level, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay locked loop updates the delay code at any time to adjust internal timing with temperature changes, then the timing adjustment capability is improved, but the power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling the delay locked loop to update delay codes only during specific time windows (within refresh cycles) rather than continuously. The enable signal is activated periodically at predetermined timings to allow delay code updates, and deactivated otherwise. This periodic enabling approach maintains the ability to adjust timing with temperature changes while significantly reducing power consumption by keeping the delay locked loop in a low-power state during intervals between update opportunities.
2Speed
If the delay locked loop is enabled continuously to update delay code in real-time, then the response speed to temperature changes is improved, but the power consumption increases
Solution Approach 1:
The patent applies dynamics by making the enable signal dynamic rather than static. The enable signal transitions between active and inactive states based on predetermined timings and refresh cycles. This dynamic control allows the delay locked loop to be selectively enabled when temperature adjustment is needed and disabled during normal operation, achieving a balance between response speed and power consumption by adapting the operational state to actual needs.
Data Source
AI summary
A delay locked loop device (DLL) and an update method therefor are provided. The DLL device includes a DLL and an update circuit. The DLL is enabled according to an enable signal, thereby delaying an input clock to provide a delayed clock. The update circuit includes a flag generating circuit and an enable circuit. The flag generating circuit provides an update flag based on a default time interval. The enable circuit triggers the enable signal to a first logic level according to the update flag, and transitions the enable signal from the first logic level to a second logic level before the end of the default time interval. The default time interval is shorter than the refresh cycle of the memory.