DLL Variable Bias Circuit for Wide-Range Step Size Programmability
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) face challenges in achieving a wide frequency range of operation due to the need for duplicate hardware and associated logic for different step sizes, which increases area usage, especially in advanced technologies like 7 nm and smaller, limiting their efficiency in applications such as High Bandwidth memory and DDR5.
Innovation Solution
The implementation of a variable bias generation circuit using a stacked or parallel architecture with a pair of transistor sets controlled by a step size signal, allowing for dynamic adjustment of bias current and step size, enabling the same delay lines to be used for both high and low frequencies, thus reducing area usage and enhancing programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If duplicate hardware and associated logic are used for different step sizes, then high frequency and low frequency applications can be supported, but the area usage increases significantly
Solution Approach 1:
The delay line is designed to be universal and support multiple functions by accommodating both high frequency (small step size) and low frequency (large step size) operations through a single hardware structure. The same delay line infrastructure is reused across different frequency ranges by dynamically adjusting the step size control signals, eliminating the need for separate duplicate hardware for different frequency applications.
Solution Approach 2:
The step size is made dynamically adjustable through control signals that can switch between different step size modes (e.g., 2ps-100ps for high frequency, 20ps-400ps for low frequency). This dynamic configuration allows the same hardware to adapt its behavior based on the operating frequency requirements, resolving the contradiction between versatility and area usage.
2Measurement precision
If small step sizes are used for high frequency applications, then accurate data sampling is achieved, but the delay range programmability is limited for low frequency applications
Solution Approach 1:
The step size is dynamically configurable based on the operating frequency. For high frequency applications, the system selects small step sizes (2ps-100ps) to achieve accurate data sampling. For low frequency applications, the system switches to large step sizes (20ps-400ps) to provide adequate delay range programmability. This dynamic adaptation resolves the contradiction between measurement precision and adaptability.
Solution Approach 2:
The step size parameter is changed based on the operating frequency requirements. The system implements multiple step size ranges (fine step size for high frequency, coarse step size for low frequency) and switches between them using control logic. This parameter change strategy allows the delay line to maintain optimal performance across different frequency applications without requiring separate hardware for each case.
3Adaptability or versatility
If large step sizes are used for low frequency applications, then wide delay range is achieved, but the data sampling accuracy deteriorates for high frequency applications
Solution Approach 1:
The system dynamically adjusts the step size based on the operating frequency to resolve the contradiction between delay range and sampling accuracy. For low frequency applications where wide delay range is critical, large step sizes (20ps-400ps) are selected. For high frequency applications where sampling accuracy is paramount, the system switches to small step sizes (2ps-100ps). This dynamic parameter adjustment ensures optimal performance for each operating condition.
Data Source
AI summary
Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.