Variable Delay Units in DLL for Semiconductor Memory
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Solution Overview
Problem
Conventional DRAMs face challenges in completing the DLL sequence within a predetermined execution period due to extended lock times caused by temperature variations, leading to delayed execution of subsequent DLL sequences.
Innovation Solution
The proposed delay locked loop (DLL) includes a DLL control circuit and a delay line circuit with a variable number of delay units, each containing a different number of delay elements. This configuration allows for efficient delay adjustment by activating delay units with more stages of NAND gates as needed, thereby reducing lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DLL delay operation is performed to adjust the internal clock signal delay, then the clock synchronization is improved, but the lock time is extended beyond the predetermined execution period
Solution Approach 1:
The delay line circuit is divided into multiple delay units, each with a different number of delay elements. This segmentation allows the DLL to selectively activate only the necessary delay units based on the required delay amount, rather than sequentially activating all delay units. The patent divides the delay line into units with varying numbers of NAND gates (e.g., 2, 4, 6, 8 gates), enabling finer-grained control over delay adjustment and reducing the total time required to achieve lock.
Solution Approach 2:
The delay line circuit employs a dynamic configuration where the number of delay elements in each delay unit varies. This dynamic structure allows the system to adaptively select the appropriate delay units based on the required delay amount. The patent implements this by creating delay units with different numbers of NAND gates, enabling the DLL to dynamically adjust the delay path to match the required delay, thereby reducing lock time while maintaining synchronization precision.
2Temperature
If the clock cycle is extended due to temperature variations, then the inherent delay time is exceeded, but the total execution time of the DLL sequence is extended
Solution Approach 1:
The delay line is segmented into multiple delay units with different numbers of delay elements, allowing the system to compensate for temperature-induced clock cycle variations by selectively activating the appropriate number of delay units. This segmentation enables fine-grained adjustment of the delay path to match the varying inherent delay time caused by temperature changes, without requiring sequential activation of all delay units, thus maintaining quick lock times despite temperature compensation needs.
Solution Approach 2:
The system changes the delay parameter by selecting different combinations of delay units based on the required delay amount and temperature conditions. The patent implements parameter changes by varying the number of active delay units and their configuration (different numbers of NAND gates per unit) to adjust the total delay, allowing the DLL to adapt to temperature variations while maintaining execution within the predetermined period.
3Measurement precision
If more delay units are activated to achieve the required delay, then the delay precision is improved, but the lock time is extended
Solution Approach 1:
The delay line is divided into multiple delay units with different numbers of delay elements (e.g., units with 2, 4, 6, 8 NAND gates). This segmentation allows the system to achieve precise delay adjustment by selectively activating only the necessary delay units based on the required delay amount, rather than activating all delay units sequentially. The fine-grained segmentation enables the DLL to achieve the required delay precision with fewer activated units, thereby reducing lock time.
Solution Approach 2:
Different delay units have different local qualities in terms of the number of delay elements they contain. This local quality variation allows the system to optimize the delay path by selecting units with appropriate delay characteristics for the specific delay amount required. The patent implements this by creating delay units with varying numbers of NAND gates, enabling the DLL to locally optimize each delay unit's contribution to the total delay, achieving precision without requiring full activation of all units.
Data Source
AI summary
The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.