DLL-Based Time-to-Digital Circuit for Stable Vernier Delay Measurement
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Solution Overview
Problem
The accuracy of time-to-digital conversion in 2D-vernier type time-to-digital conversion circuits is compromised due to variations in delay elements, such as process variations, temperature, and voltage, which affect the delay time accuracy and resolution.
Innovation Solution
Incorporating a first and second delay locked loop (DLL) circuit in the circuit device, with a comparator array section for phase comparison, and using clock signals generated by resonators to adjust delay elements, thereby reducing the influence of variations and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay elements are used in a 2D-vernier type time-to-digital conversion circuit to achieve fine time resolution, then measurement precision is improved, but manufacturing precision deteriorates due to process variations affecting delay time accuracy
Solution Approach 1:
The patent introduces feedback mechanisms through delay-locked loops (DLLs) that continuously monitor and adjust the delay times of delay elements. The DLL circuits compare the actual delay time with a reference and generate control signals to compensate for variations, thereby maintaining consistent delay times across different manufacturing processes and environmental conditions.
Solution Approach 2:
The patent employs temperature compensation techniques that dynamically adjust the operating parameters of delay elements based on detected temperature variations. By changing parameters such as bias currents or control voltages in response to temperature changes, the system compensates for thermal effects on delay time, maintaining manufacturing precision across different operating temperatures.
2Measurement precision
If delay elements are used to achieve fine time resolution, then measurement precision is improved, but reliability deteriorates due to sensitivity to temperature and voltage variations
Solution Approach 1:
The delay-locked loops continuously monitor delay times and generate feedback control signals that adjust the delay elements in real-time. This feedback mechanism compensates for drift caused by temperature and voltage variations, maintaining reliable and stable delay times despite environmental changes.
Solution Approach 2:
The patent implements pre-compensation techniques where the system anticipates and counteracts the effects of temperature and voltage variations before they significantly impact delay times. By detecting early signs of environmental changes and adjusting delay element parameters in advance, the system cushions against potential reliability issues.
3Measurement precision
If a 2D-vernier type time-to-digital conversion circuit is used to achieve high measurement precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the time-to-digital conversion function into multiple independent delay circuits arranged in a two-dimensional vernier configuration. Each delay circuit handles a specific portion of the measurement range, and the combined output achieves high precision. This segmentation allows each individual circuit to remain relatively simple while the overall system achieves high measurement precision.
Solution Approach 2:
The delay elements are designed to serve multiple functions: they provide the primary delay function for time measurement, act as variable delay elements controlled by DLL feedback, and serve as temperature-compensated elements. This multi-functionality reduces the need for separate compensation circuits, thereby managing device complexity while maintaining high measurement precision.
Data Source
AI summary
A circuit device includes a first circuit, a second circuit, and a comparator array section. The first circuit has a first DLL circuit having a plurality of delay elements, and delays a first signal. The second circuit has a second DLL circuit having a plurality of delay elements, and delays a second signal. The comparator array section has a plurality of phase comparators arranged in a matrix, the first delayed signal group from the first circuit and the second delayed signal group from the second circuit are input to the comparator array section, and the comparator array section outputs a digital signal corresponding to a time difference in the transition timing between the first signal and the second signal.