Voltage Providing Circuit for DLL Stand-by Mode Transition
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Solution Overview
Problem
The conventional signal delaying system experiences a time delay when transitioning from a stand-by mode to a normal mode due to the difference between control voltage and stand-by voltage in the DLL circuit, leading to inefficiencies in memory operations.
Innovation Solution
A signal delaying system that includes a DLL circuit and a voltage providing circuit, which adjusts the stand-by voltage to be substantially equal to the control voltage, using a circuit architecture that comprises a stand-by voltage providing circuit, a switch element, a control circuit, a control voltage providing circuit, and an adjusting circuit to ensure voltage equality across modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a stand-by voltage is provided to the DLL circuit while stopping the DLL voltage in stand-by mode, then power consumption is reduced, but a time delay occurs when transitioning back to normal mode due to voltage difference
Solution Approach 1:
The adjusting circuit performs preliminary action by adjusting the stand-by voltage to be substantially equal to the control voltage before the DLL circuit transitions from stand-by mode to normal mode. This preliminary voltage alignment eliminates the need for voltage adjustment during mode transition, thereby removing the transition delay while maintaining power savings during stand-by operation.
2Speed
If the control voltage is maintained higher than the stand-by voltage, then the DLL circuit can quickly resume operation, but power consumption increases during stand-by mode
Solution Approach 1:
The adjusting circuit performs preliminary voltage adjustment during stand-by mode to set the stand-by voltage equal to the control voltage. This preliminary action allows the DLL circuit to resume operation immediately upon mode transition without requiring additional voltage adjustment time, while the voltage adjustment is performed during stand-by when power consumption is already reduced.
Data Source
AI summary
A signal delaying system is provided, including a delay locked loop circuit and a voltage providing circuit. The delay locked loop circuit delays an input signal to generate a delayed signal. The voltage providing circuit provides a control voltage to the delay locked loop circuit for determining a delay time of the delay locked loop circuit when the delay locked loop circuit operates in a first mode; and providing a stand-by voltage to the delay locked loop circuit when the delay locked loop circuit operates in a second mode, wherein the voltage providing circuit further adjusts the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.