Direct Memory Access Adaptor for Chip-to-Chip Data Transfer

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current systems for processing frames or payloads by network adaptor chips lead to increased host CPU utilization, latency, and PCIe Root Complex and host server memory bandwidth requirements, as they necessitate host CPU orchestration of header descriptors and payloads between adaptor chips.

Innovation Solution

Implementing a self-contained system that enables direct chip-to-chip data transmission via PCIe fabric, bypassing host CPU intervention by using non-host memory and DMA operations, with phase state bits to ensure valid data transfer, thereby reducing CPU utilization, latency, and bandwidth requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If host CPU orchestrates the transfer of header descriptors and payloads between adaptor chips, then data transfer can be completed, but host CPU utilization increases

Engineering Contradiction:

Improvedata transfer completionVSAvoidhost CPU utilization

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The source adaptor chip autonomously transfers header descriptors and payloads to the destination adaptor chip using DMA operations without requiring host CPU intervention. The adaptors self-manage the data transfer process by directly accessing PCIe fabric and exchanging data packets, thereby reducing host CPU utilization while maintaining data transfer productivity.

Inventive Principle:

Principle #25Self-service

2Productivity

If host CPU orchestrates the transfer of header descriptors and payloads between adaptor chips, then data transfer can be completed, but latency of payload transfer increases

Engineering Contradiction:

Improvedata transfer completionVSAvoidlatency of payload transfer

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The host CPU is extracted from the data transfer path between adaptor chips. By removing the host CPU orchestration step, the system enables direct peer-to-peer communication between source and destination adaptors through PCIe fabric, thereby completing data transfer while eliminating the time delay introduced by CPU intervention.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If host CPU orchestrates the transfer of header descriptors and payloads between adaptor chips, then data transfer can be completed, but PCIe Root Complex and host server memory bandwidth requirements increase

Engineering Contradiction:

Improvedata transfer completionVSAvoidPCIe Root Complex and host server memory bandwidth requirements

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The adaptor chips independently manage their own data transfers using local memory and DMA engines, eliminating the need to burden the host server memory and PCIe Root Complex with every data transfer operation. This self-service approach reduces the bandwidth requirements on shared host resources while maintaining complete data transfer functionality.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10664420B2System and method for port-to-port communications using direct memory access

Publication Date: 2020.05.26 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A system, method, and adaptor that facilitate data transmission are described. One example of the disclosed system facilitates the chip-to-chip transport of header descriptors and payloads. The system may include a source chip, a destination chip, and a set of queues describing buffer memory locations for staging header descriptors and payloads to be transferred from the source chip to the destination chip, where the set of queues are directly accessible to the source chip and to the destination chip.