DMA Address Generation for In-Memory Interleaving in DSP SoCs
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Solution Overview
Problem
Digital signal processing systems face inefficiencies due to the need for dedicated memory for interleaving and deinterleaving operations, which results in underutilization of memory resources when handling different digital television and radio standards with varying memory demands.
Innovation Solution
A digital signal processing system-on-chip with a shared on-chip memory and a configurable direct memory access (DMA) controller that generates non-linear memory address sequences, allowing interleaving and deinterleaving operations to be performed during data transfer without requiring dedicated memory, thereby optimizing memory usage across different standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dedicated memory device is allocated for interleaving/deinterleaving operations, then the memory can handle the standard with the largest memory demands, but the memory is frequently underutilised when handling other standards with lower memory demands
Solution Approach 1:
The patent applies universality by enabling the DMA controller's address generator to perform multiple functions: it can generate both linear and non-linear address sequences, allowing the same memory resource to serve both general data transfer and dedicated interleaving/deinterleaving operations. This eliminates the need for separate dedicated memory for interleaving operations, as the shared memory can be dynamically reconfigured through different address generation modes to handle different standards efficiently.
2Productivity
If a dedicated memory device is allocated for interleaving operations, then interleaving/deinterleaving can be performed efficiently, but silicon area is consumed by the dedicated memory
Solution Approach 1:
The patent merges the interleaving/deinterleaving functionality with the general-purpose DMA controller by equipping it with a configurable address generator. This allows interleaving operations to be performed using the same memory infrastructure as other data transfers, combining multiple functions into a single integrated system rather than requiring separate dedicated memory resources.
Solution Approach 2:
The address generator can dynamically change its addressing parameters between linear and non-linear modes depending on the operation required. By modifying the address generation parameters rather than requiring dedicated hardware, the system achieves efficient interleaving operations without consuming additional silicon area for separate memory resources.
3Adaptability or versatility
If a configurable address generator is used to generate non-linear address sequences, then interleaving/deinterleaving can be performed during data transfer without dedicated memory, but the device complexity increases
Solution Approach 1:
The address generator is designed to be dynamically configurable, allowing it to switch between linear and non-linear addressing modes as needed. This dynamic capability enables the same hardware to adapt to different operational requirements (general data transfer vs. interleaving operations) without requiring multiple dedicated hardware paths, thereby managing complexity while maintaining flexibility.
Data Source
AI summary
Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.