DMA Queue Arbitration Using Block Fragmentation for Fair Scheduling
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Solution Overview
Problem
Conventional direct memory access (DMA) techniques face inefficiencies due to the potential for one queue to be idle while processing large data blocks, leading to delayed processing of smaller data blocks in other queues, which diminishes data transfer efficiency.
Innovation Solution
The implementation of a DMA engine with a DMA data arbiter and fragmenter that regulates and splits large data blocks into smaller ones, ensuring timely processing of data across multiple queues, thereby preventing any single queue from being starved and maintaining efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA techniques process large data blocks from one queue, then data transfer capacity is improved, but other queues may be starved and experience excessive idle time
Solution Approach 1:
The patent segments the DMA processing into multiple independent queues (e.g., queue 0 for large data blocks, queue 1 for small data blocks). The segmentation allows different queue types to be handled separately, preventing large data block processing from blocking small data block processing, thus reducing queue idle time while maintaining high data transfer capacity
Solution Approach 2:
The patent implements dynamic queue selection and arbitration mechanisms that adaptively switch between processing different queues based on current system conditions, data block sizes, and queue priorities. This dynamic approach ensures that when one queue is being serviced, other queues can be processed in between, minimizing idle time across all queues
2Ease of operation
If the processor is used to transfer data to and from memory, then data transfer control is simplified, but the processor cannot perform other functions and processing speed decreases
Solution Approach 1:
The patent extracts the data transfer function from the main processor by implementing a separate DMA (Direct Memory Access) controller. This extraction allows the processor to focus on computation tasks while the DMA controller handles data transfer operations independently, thereby maintaining simplified transfer control while significantly improving overall system processing speed
Solution Approach 2:
The patent introduces a DMA controller as an intermediary between the processor and memory system. This intermediary handles all data transfer operations, including queue arbitration and data block processing, allowing the processor to remain free for other functions while maintaining efficient and controlled data transfer through the DMA intermediary
Data Source
AI summary
A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.