DMA Bridge Controller for Asynchronous Multi-Subsystem Data Transfer
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Solution Overview
Problem
In electronic systems with multiple subsystems, speed differences between subsystems result in reduced data transfer performance when one subsystem accesses another through a bridge, necessitating a solution for optimal data transfer.
Innovation Solution
A data transmission controller with bridging and Direct Memory Access (DMA) functions, comprising masters, slaves, channels, and command converters, that convert commands and data based on data flow directions to facilitate efficient data transfer between and within subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bridge is used to connect subsystems with different speeds, then subsystems can access each other, but data transfer performance is reduced
Solution Approach 1:
The patent introduces a bridge controller as an intermediary device between subsystems with different speeds. The bridge controller includes command converters that translate commands between different subsystem protocols and a DMA controller that manages data transfer buffering, allowing subsystems with different speeds to communicate while maintaining optimal transfer performance through intermediate processing.
Solution Approach 2:
The bridge controller is segmented into distinct functional modules: command converters for protocol translation, DMA controller for transfer management, and channel controllers for individual data paths. This segmentation allows each module to optimize its specific function, improving overall data transfer performance while maintaining subsystem compatibility.
2Stability of the object's composition
If a bridge is used for asynchronous processing between subsystems, then speed differences are handled, but transfer performance is reduced
Solution Approach 1:
The command converters perform preliminary command translation and validation before data transfer begins. The DMA controller pre-configures transfer parameters and buffers data in advance, allowing asynchronous processing to proceed smoothly without real-time speed matching, thereby maintaining both stability and performance.
Solution Approach 2:
The bridge controller implements feedback mechanisms where the DMA controller monitors transfer status and adjusts buffering strategies based on subsystem readiness. Command converters receive feedback about command execution status and adapt translation processes, enabling efficient asynchronous processing that maintains high transfer performance.
Data Source
AI summary
A data transmission controller including a first master, a second master, a first slave, a second slave, a plurality of channels, a direct memory access (DMA) controller, a first command converter, and a second command converter is provided. The channels are coupled to the first or second master. The DMA controller is configured to receive a plurality of first commands, and to transmit the first commands to the channels corresponding to different data flow directions in order to transmit the first commands to the first or second master. The first and second command converters are respectively connected to the first and second slave, and are respectively connected to the second and first master through the channels. The first and second command converters are configured to convert original commands into a plurality of second commands with DMA mode.