DMA Buffer Pool Thread Key Assignment for Packet Processing
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Solution Overview
Problem
Traditional network and storage systems in cloud computing architectures face performance and administrative bottlenecks, particularly in managing packet processing and buffer utilization in high-performance networking devices with limited CPU and memory resources.
Innovation Solution
A system that employs a thread scheduling engine to assign thread keys for DMA resource access, utilizing a pool of direct memory access resources and packet buffers organized in linked lists or linear arrays, allowing multiple threads to concurrently access buffers without locking mechanisms, optimizing buffer utilization and packet processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional network and storage systems are used in cloud computing architectures, then system stability is maintained, but performance bottlenecks and administrative overhead increase significantly
Solution Approach 1:
The DMA engine performs packet processing autonomously without requiring CPU intervention for each packet. The system configures the DMA engine with buffer addresses and control parameters, then the DMA engine independently executes packet transfer and processing operations, reducing administrative overhead while improving throughput
Solution Approach 2:
The patent extracts packet processing functionality from the CPU and relocates it to a dedicated DMA engine. This separation allows the CPU to focus on higher-level tasks while the DMA engine handles low-level packet processing, reducing both performance bottlenecks and administrative complexity
2Productivity
If multiple software threads share DMA resources, then resource utilization efficiency improves, but resource contention and access coordination complexity increase
Solution Approach 1:
The patent introduces a descriptor ring as an intermediary structure between multiple software threads and the shared DMA engine. Each thread submits packet processing requests to the descriptor ring, which organizes and queues these requests. The DMA engine then processes packets from the descriptor ring in an orderly fashion, enabling efficient multi-threaded access without direct thread-DMA interaction complexity
Solution Approach 2:
The patent segments the packet processing workflow into distinct phases: thread-level packet preparation, descriptor ring queuing, and DMA engine execution. This segmentation allows multiple threads to work independently on packet preparation while the DMA engine handles execution, reducing resource contention through temporal and functional separation
3Reliability
If packet buffers are managed using traditional locking mechanisms, then buffer access safety is ensured, but CPU overhead and processing performance decrease
Solution Approach 1:
The DMA engine autonomously manages packet buffer access according to pre-configured parameters in the descriptor ring. It independently reads packet data from source buffers and writes to destination buffers without requiring CPU-mediated locking. This self-service approach ensures buffer access safety through hardware-enforced protocols while eliminating CPU overhead associated with software locking mechanisms
Solution Approach 2:
The patent replaces software-based locking mechanisms (mechanical system) with hardware-based DMA engine control. The DMA engine uses dedicated control registers and status flags to manage buffer access, substituting complex software synchronization with simpler hardware-controlled access patterns that maintain safety without CPU intervention
4Productivity
If a large number of packet buffers are allocated in memory, then packet processing capacity increases, but memory footprint and system resource consumption increase
Solution Approach 1:
The patent implements dynamic buffer management where the DMA engine processes packets from a pool of buffers and returns processed buffers to the pool for reuse. The descriptor ring dynamically tracks buffer states (available, being processed, completed), allowing the system to maintain a compact buffer pool that adapts to varying packet processing demands rather than allocating fixed large memory regions
Solution Approach 2:
The system recovers and reuses packet buffers after DMA processing completes. Processed buffers are marked as available in the descriptor ring and can be immediately reused for new packet transfers. This recovery mechanism eliminates the need to allocate new buffers for each packet, increasing processing capacity while maintaining a limited memory footprint
Data Source
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AI summary
A system and method can support efficient packet processing in a network environment. The system can comprise a direct memory access (DMA) resources pool that comprises one or more of DMA resources. Furthermore, the system can use a plurality of packet buffers in a memory, wherein each said DMA resource can point to a chain of packet buffers in the memory. Here, the chain of packet buffers can be implemented based on either a linked list data structure and/or a linear array data structure. Additionally, each said DMA resource allows a packet processing thread to access the chain of packet buffers using a pre-assigned thread key.