DMA Buffer Staging for Heterogeneous Processor Transfer
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Solution Overview
Problem
Existing heterogeneous processing systems face challenges in efficiently transferring data between multiple processors due to the need for asynchronous data exchange and lack of support for parallel and pipelined execution of applications, particularly in machine learning and artificial intelligence programs.
Innovation Solution
A heterogeneous processing system with a host processor, multiple processors, and data transfer resources, utilizing a common buffer space and DMA engines for efficient data transfer, enabling dynamic selection of data passing methods based on latency and bandwidth requirements, and supporting parallel and pipelined computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between multiple processors using traditional memory access methods, then data exchange can be achieved, but transfer efficiency is low and asynchronous execution is not supported
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between processors. The buffer memory receives data from a first processor and transfers it to a second processor, enabling asynchronous data exchange. This intermediary allows producers and consumers to operate at different speeds and times, resolving the contradiction between transfer efficiency and transfer time by decoupling the data exchange process from direct processor synchronization.
2Productivity
If multiple processors are used for parallel execution, then computation speed increases, but data coordination and transfer complexity increases
Solution Approach 1:
The patent segments the data transfer function from the processing function by introducing dedicated buffer memories for each processor. Each buffer memory is independently configured and managed, allowing processors to execute in parallel without complex inter-processor coordination. This segmentation isolates data transfer operations, reducing the overall system complexity while maintaining parallel computation speed.
3Reliability
If data is transferred synchronously between processors, then data consistency is maintained, but parallel and pipelined execution is blocked
Solution Approach 1:
The patent implements dynamic data transfer by allowing buffer memories to operate independently with flexible timing. The buffer memory can accept data from one processor and transfer it to another processor at different times, enabling asynchronous operations. This dynamic approach maintains data consistency through proper buffering while allowing parallel and pipelined execution to proceed without synchronous blocking.
4Adaptability or versatility
If application-level programming is used to manage data transfer, then flexibility is achieved, but programming complexity and development time increase
Solution Approach 1:
The patent implements self-service data transfer through automatically configured buffer memories. The buffer memories are pre-configured with appropriate sizes and parameters based on application requirements, and they automatically manage data transfer operations without requiring detailed application-level programming. This self-service approach maintains flexibility through configurable parameters while reducing programming complexity by eliminating the need for manual data transfer management code.
Data Source
AI summary
A heterogeneous processing system and method including a host processor with a host memory having allocated buffer space, first and second processors each with memory, multiple data transfer resources, and switch and bus circuitry that communicatively couples the processors and the transfer resources. The first processor executes a first part of an application generating first data stored into the first memory. A data transfer resource is programed to transfer the first data to the buffer space and to transfer the first data from the buffer space into the second memory. The second processor executes a second part of the application generating second data stored into the second memory. The data transfer resources may include a DMA engine in which the buffer space is DMA addressable. One of the first and second processors may be a reconfigurable processor, a compute engine, or a reconfigurable dataflow unit.