DMA Controller Burst Bandwidth Arbitration
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Solution Overview
Problem
In embedded systems, low-priority agents can occupy the bus for extended periods during burst operations, preventing other modules from accessing the bus bandwidth effectively, leading to delayed servicing of high-priority requests.
Innovation Solution
The method involves splitting burst operations into separate transactions, allowing programmable channel arbitration schemes such as round-robin and fixed priority schemes, enabling interruptible and resumable data transfers, and controlling the DMA controller to manage these transactions by setting bits in control registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If burst operations are used for fast data transfer, then transfer speed is improved, but bus availability for other modules deteriorates
Solution Approach 1:
The patent divides a burst operation into multiple individual transactions, each of which can be independently arbitrated. This segmentation allows the bus to be released between transactions, enabling other modules to access the bus while maintaining the overall data transfer functionality.
2Reliability
If low priority agents are allowed to occupy the bus during burst operations, then their transfer completeness is improved, but high priority request servicing deteriorates
Solution Approach 1:
The patent implements dynamic arbitration where the bus grant can be reassigned between transactions based on current priority needs. Low priority agents can complete their transactions when the bus is available, but high priority requests can preempt or interleave with lower priority transactions, ensuring both completeness and responsiveness.
3Loss of time
If bus bandwidth is shared among modules, then bus availability is improved, but transfer speed for individual channels deteriorates
Solution Approach 1:
The patent enables periodic arbitration cycles where bus access is granted in discrete time slots or transactions rather than continuous bursts. This periodic structure allows fair sharing among multiple modules while maintaining adequate transfer speeds within each allocated time slot.
Data Source
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AI summary
An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.