DMA Bus Bridge Latency Reduction via Programmable FIFO Thresholds
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Solution Overview
Problem
In System-on-Chip (SoC) designs, slower peripheral devices can throttle throughput and introduce latency when interfaced with high-speed devices, affecting overall system performance.
Innovation Solution
The implementation of a DMA bus bridge with FIFO devices and programmable hardware that adjusts threshold values to minimize access latency, ensuring smooth operation between high-speed and low-speed peripherals by using separate frequency domains and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If slower peripheral devices are interfaced with high-speed DMA bus, then device compatibility is improved, but access latency increases
Solution Approach 1:
A bus bridge is introduced as an intermediary component between the slow peripheral device and the high-speed DMA bus. The bus bridge includes FIFO buffers that act as a mediator to absorb timing differences, allowing the peripheral to operate at its own speed while the DMA bus operates at high speed without direct connection conflicts.
Solution Approach 2:
Data is pre-loaded into the FIFO buffer before the actual transfer begins. The bus bridge prepares data in advance in the buffer, so when the DMA bus is ready, data is already available for immediate transfer, reducing the latency that would otherwise occur while waiting for the peripheral to prepare data.
2Productivity
If FIFO buffering is used to interface slow peripherals, then throughput is maintained, but initial latency increases
Solution Approach 1:
The system performs preliminary actions by pre-loading data into the FIFO buffer before the actual DMA transfer begins. This allows the DMA bus to start transferring data immediately without waiting for the peripheral to prepare each data word sequentially, thereby maintaining high throughput while minimizing initial latency.
Solution Approach 2:
The FIFO buffer enables continuous data transfer by maintaining a queue of data ready for transfer. Once data is loaded into the buffer, the DMA bus can continuously read from the buffer without interruption or waiting for the peripheral, ensuring continuous useful action and eliminating idle waiting time during the transfer process.
3Loss of time
If threshold requirements are optimized, then access latency is reduced, but system adaptability decreases
Solution Approach 1:
The bus bridge includes programmable threshold registers that can be dynamically adjusted based on different peripheral devices and transfer requirements. This dynamic configurability allows the system to optimize threshold values for minimum latency while adapting to different peripheral speeds and data transfer patterns, maintaining both low latency and system adaptability.
Solution Approach 2:
The system changes parameters by allowing programmable adjustment of threshold values in the bus bridge. Different threshold values can be programmed depending on the specific peripheral device being interfaced, enabling optimization of access latency for each device while maintaining the ability to adapt to varying system requirements through parameter reconfiguration.
Data Source
AI summary
A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.