DMA Write Steering to Cache Memory via Bus Interface
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Solution Overview
Problem
Current methods for data transfer from peripherals to processors in computing systems are inefficient, as they often rely on direct memory access (DMA) controllers writing data to system RAM, which does not provide the fastest access to processors, especially for time-sensitive or frequently accessed data.
Innovation Solution
A computing system with multiple cache memories and a bus interface that selects an appropriate cache bank for DMA write instructions based on transaction packets, allowing for faster access by determining if the packet includes preferred cache memories and banks, and managing cache usage through a credit system to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DMA controller writes data to system RAM, then data transfer is facilitated, but access speed to processor is not optimized
Solution Approach 1:
The patent introduces cache memory as an intermediary between the DMA controller and system RAM. The bus interface steers DMA write requests to appropriate cache banks, which act as a mediator that stores data closer to the processor, enabling faster access while maintaining efficient data transfer from peripherals.
Solution Approach 2:
The cache memory is divided into multiple cache banks that can be selectively accessed. The bus interface determines which cache bank should receive data based on the transaction packet, enabling parallel and optimized data storage across different cache segments, thereby improving both access speed and transfer efficiency.
2Speed
If cache memory is used for data storage, then processor access speed is improved, but cache memory management complexity increases
Solution Approach 1:
The bus interface autonomously determines which cache bank should receive data based on the transaction packet contents, without requiring complex manual management. The system self-manages cache allocation by evaluating packet characteristics and automatically steering requests to appropriate banks, reducing management complexity while maintaining high access speeds.
3Productivity
If DMA writes directly to RAM, then system simplicity is maintained, but data transfer optimization is lost
Solution Approach 1:
The patent merges the cache memory subsystem with the existing DMA controller and bus interface. The bus interface integrates cache bank selection logic directly into the data path, combining multiple functions (DMA control, cache management, data steering) into a unified architecture that optimizes data transfer without proportionally increasing system complexity.
Data Source
AI summary
A system may include a processor which may include a cache memory and a Direct Memory Access (DMA) controller, a peripheral device on an I/O expansion bus, and a bus interface coupled to the I/O expansion bus and the processor. The bus controller may determine if data packets sent from the peripheral device to the processor include a DMA write instruction to the cache memory with an optional desired cache location. Upon determining a DMA write instruction to the cache memory is included in the data packet, the bus controller may format the data in the data packet for storage in the cache and either receive the desired cache location or determine an appropriate location within the cache to store the formatted data. The bus controller may determine an alternate location within the cache if the desired location within the cache cannot accept more data from the peripheral device.