DMA Cache Coherence Using Dirty-Line Skip Writes in L2 Memory
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Solution Overview
Problem
In digital signal processors, maintaining coherence between CPU and DMA access to level two memory is inefficient, leading to performance issues and increased dynamic power consumption due to unnecessary updates in the level two memory during DMA writes.
Innovation Solution
The solution optimizes DMA writes by not updating the level two memory when a line is valid and dirty in level one memory, allowing level one memory to handle writeback at a later time, thereby reducing the number of DMA writes to level two directly addressable memory and minimizing dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DMA writes update level two memory to maintain coherence, then coherence between CPU and DMA access is maintained, but performance decreases and dynamic power consumption increases due to unnecessary updates
Solution Approach 1:
The patent applies partial action by selectively updating level two memory only when necessary. The level two controller checks the valid and dirty status of cache lines in level one memory before performing DMA writes. When a line is valid and dirty, the update is skipped since level one will eventually writeback the changes. This partial updating approach maintains coherence while reducing unnecessary writes to level two memory, thereby improving performance and reducing power consumption.
2Reliability
If DMA writes update level two memory to maintain coherence, then coherence between CPU and DMA access is maintained, but dynamic power consumption increases due to unnecessary updates
Solution Approach 1:
The patent reduces dynamic power consumption by performing partial updates to level two memory. The level two controller evaluates the valid and dirty status of corresponding cache lines in level one memory before executing DMA writes. When both conditions indicate the line is valid and dirty, the controller skips the update operation, knowing that level one will perform a writeback when the line is evicted. This selective updating minimizes unnecessary memory operations and associated power consumption while preserving data coherence.
3Productivity
If DMA writes skip updating level two memory when line is valid and dirty, then performance improves and power consumption decreases, but coherence maintenance becomes more complex
Solution Approach 1:
The patent employs feedback mechanisms through status flags (valid and dirty bits) associated with each cache line in level one memory. The level two controller continuously monitors these flags to determine whether DMA writes should update level two memory. This feedback-driven approach automates the coherence maintenance decision process, reducing the perceived complexity for software developers while internally managing the sophisticated coherence protocol required for the selective update strategy.
4Productivity
If DMA writes skip updating level two memory when line is valid and dirty, then level two memory is freed for other requestors, but additional writeback operations are required in level one
Solution Approach 1:
The patent uses preliminary action by having level one memory maintain dirty status flags that indicate which cache lines contain modified data not yet written to level two memory. This preliminary tracking allows the system to defer writeback operations until the cache line is evicted and needs to be replaced. By preparing and tracking the status of cache lines in advance, the system can efficiently manage writeback operations without incurring performance penalties, as the writeback is naturally triggered during the normal cache replacement process rather than requiring additional dedicated operations.
Data Source
AI summary
This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.