DMA Circuitry Bypassing Bus Interface Polling
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Solution Overview
Problem
Polling for events in direct memory access (DMA) transfers between the CPU and peripheral components competes for interface bandwidth, increasing latency and decreasing throughput due to the involvement of the bus interface in coordinating these transfers.
Innovation Solution
A DMA circuit arrangement that polls a register for buffer addresses in main memory to initiate data transfers and writes event data to main memory upon transfer completion, eliminating the need for bus interface polling by the host and peripheral component, and using multiple buffers for egress and ingress data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polling for events is performed over the bus interface between CPU and peripheral component, then coordination of DMA transfers is achieved, but interface bandwidth is consumed and latency increases
Solution Approach 1:
The patent segments the event coordination function from the data transfer path by implementing separate event registers in the peripheral component and corresponding event buffers in main memory. This allows event polling to occur independently in main memory without consuming bus interface bandwidth that is needed for actual data transfers.
Solution Approach 2:
The patent introduces main memory as an intermediary for event communication. Instead of direct polling between CPU and peripheral component over the bus interface, event data is written to main memory by the peripheral component, and the CPU polls these event buffers in main memory, eliminating the need for bus interface polling.
2Reliability
If polling for events is performed over the bus interface, then DMA transfer coordination is maintained, but DMA throughput decreases due to bandwidth competition
Solution Approach 1:
The patent separates event signaling from data transfer operations by implementing dedicated event registers in the peripheral component and corresponding event buffers in main memory. This segmentation allows DMA data transfers to utilize the full bus interface bandwidth without competing with event polling operations.
Solution Approach 2:
Main memory serves as an intermediary that decouples event coordination from the bus interface data path. The peripheral component writes event data to main memory buffers, and the CPU polls these buffers without using the bus interface, thereby eliminating bandwidth competition and maximizing DMA throughput.
3Device complexity
If the bus interface is used for both data transfers and event polling, then a single interface is sufficient, but bandwidth is shared and performance is reduced
Solution Approach 1:
The patent segments the communication functions by implementing separate event registers in the peripheral component and dedicated event buffers in main memory. This allows event polling to occur through a different path (main memory access) than data transfers (bus interface), effectively creating logical separation without adding physical interface complexity.
Solution Approach 2:
The patent utilizes main memory for dual purposes: storing both data to be transferred and event data for coordination. This multi-functional use of main memory eliminates the need for separate communication interfaces or additional polling mechanisms, maintaining interface simplicity while improving bandwidth availability for data transfers.
Data Source
AI summary
Disclosed approaches eliminate involving a bus interface in polling by the host computer system and the peripheral component for events to coordinate direct memory access (DMA) transfers. The host polls main memory for DMA events communicated by the peripheral component, and the peripheral component polls local registers for DMA addresses to initiate DMA transfers. DMA transfers are initiated by the host storing main memory addresses in the local registers of the peripheral component, and DMA events generated by the peripheral component are stored in the main memory.