DMA-Based CNN Backpropagation With Modular Kernel Updates

The patent merges multiple computation functions into a single integrated neural network processor that combines computation modules, memory units, and communication interfaces in one device. This eliminates the need for complex intercommunication between multiple general-purpose processors while maintaining high computational capability through parallel processing within the unified architecture.

The processor is divided into multiple computation modules that can operate independently and concurrently. Each module handles specific computational tasks, allowing parallel processing without requiring complex intercommunication between separate processors. The segmentation is implemented through independent memory access units and modular computation cores within a single chip.

The patent implements a hierarchical memory structure where small on-chip cache memory units are nested within each computation module, and these are nested within larger off-chip memory. This nested architecture allows frequent small data accesses to occur on-chip without requiring large data transfers, reducing power consumption while maintaining high storage capacity through the hierarchical structure.

The patent introduces intermediate cache memory units between the computation modules and off-chip memory. These intermediaries act as buffers that store frequently accessed model data locally, reducing the frequency of high-power off-chip memory accesses while still providing access to large storage capacities through the cache hierarchy.