Multi-Channel DMA System with Command Queue Structure
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Solution Overview
Problem
Existing data processing systems face challenges in managing multi-channel direct memory access (DMA) operations due to constraints such as form-factor, part count, power budgets, and conflicting data transfer protocols, leading to increased latency and difficulty in balancing performance demands with design constraints, especially in portable and handheld devices.
Innovation Solution
A multi-channel DMA system employing a command queue structure to support three DMA modes: direct configuration, link list configuration, and program configuration, allowing dynamic assignment of program sequences and command queue structures to contexts, enabling simultaneous operation of different modes and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple auxiliary processors are replicated to support multiple DMA channels, then DMA transfer capability and channel support are improved, but device complexity, part count, and power consumption increase
Solution Approach 1:
The patent implements a single auxiliary processor that can function as multiple virtual DMA channels through command queue structures. The auxiliary processor dynamically switches between different DMA channel contexts by loading parameters from command queues, allowing one processor to perform the work of multiple processors while supporting multiple DMA channels simultaneously.
Solution Approach 2:
The patent creates virtual copies of DMA channel contexts through command queue structures. Instead of replicating physical auxiliary processors, the system creates software-defined channel contexts that are loaded into a single auxiliary processor, enabling multiple channels to be supported through parameter copying and context switching.
2Device complexity
If a single auxiliary processor is shared amongst multiple DMA channels, then device complexity and power consumption are reduced, but context switching overhead increases DMA transfer latency
Solution Approach 1:
The patent pre-loads DMA channel parameters into command queue structures before switching is needed. Command queues contain pre-configured parameter sets for multiple DMA channels, allowing the auxiliary processor to quickly switch between channels by simply loading pre-prepared parameter blocks rather than reconfiguring registers in real-time during context switching.
Solution Approach 2:
The patent introduces command queue structures as intermediary data structures between the CPU and the auxiliary processor. These command queues act as a buffer that stores parameter sets for multiple DMA channels, allowing the auxiliary processor to efficiently switch between channels by sequentially processing command queue entries without direct CPU intervention during switching operations.
3Ease of manufacture
If traditional DMA controller architectures are used, then implementation is straightforward, but they cannot simultaneously support multiple DMA modes and suffer from context switching overhead
Solution Approach 1:
The patent implements dynamic mode switching capability where a single DMA controller can operate in different modes (traditional mode, virtual channel mode, or hybrid mode) based on system requirements. The controller dynamically configures its operation by loading different command queue structures, allowing it to adapt between simple traditional DMA operations and complex virtual channel operations without requiring separate hardware implementations.
Data Source
AI summary
A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different virtual DMA channels and stored in a command queue structure, such that a first command sequence is processed to directly configure one or more first register descriptors at a context store to implement a direct configuration DMA mode for a first virtual channel, a second command sequence is processed to initiate a fetch of a linked list descriptor chain for loading one or more second register descriptors at a second DMA channel context store register to implement a link list configuration DMA mode for a second virtual channel, and a third command sequence is processed to retrieve an instruction program for loading into the command queue structure and execution by the DMA controller to implement a program configuration DMA mode for a third virtual channel.