DMA-Based Communication Control for PLC Throughput Bottlenecks

The patent introduces a control ASIC as an intermediary device between the master communication ASIC and the processor. This control ASIC includes a communication interface, a descriptor table, and a controller that manages data transfer operations. By offloading the complex data transfer management to this intermediary control ASIC, the system achieves high throughput without requiring the main processor to have enhanced capabilities, thus resolving the contradiction between throughput improvement and processor complexity.

The patent employs parameter changes by implementing a descriptor table that stores multiple sets of transfer parameters (source address, destination address, transfer size, etc.). The controller dynamically selects and applies different parameter sets based on the specific data transfer task. This allows the system to adapt to different data transfer requirements without physically modifying the transmission path hardware, thereby improving data transfer capability while maintaining fixed transmission path specifications.

The patent segments the data transfer management function into multiple independent DMA cores (first DMA core, second DMA core, etc.), where each DMA core is responsible for handling data transfers for specific tasks or communication channels. The controller assigns specific descriptor table entries to each DMA core based on task requirements. This segmentation allows parallel data transfer operations without requiring a single complex control circuit, as each DMA core operates semi-independently with its own control logic, thus improving efficiency while keeping individual control circuits manageable.