DMA-Controlled Communication Unit for Higher PLC Data Throughput
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Solution Overview
Problem
Existing communication systems in control devices, such as programmable logic controllers (PLCs), face challenges in improving data transfer throughput due to limitations in processing capability and data transfer between the master communication ASIC and the processor, making it difficult to enhance the transmission path specification.
Innovation Solution
A control device configuration that includes a communication unit with an arithmetic processing part, a communication circuit, and a control circuit featuring multiple DMA cores and a controller that manages tasks using descriptor tables with prioritized processing, allowing for efficient data transfer between the communication unit and functional units via independent channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processing capability of the processor and master communication ASIC is improved to increase data transfer throughput, then the throughput is improved, but the device complexity and cost increase
Solution Approach 1:
The control circuit is divided into multiple independent DMA cores (first DMA core for arithmetic processing part, second DMA core for communication circuit) that can operate independently and in parallel. Each DMA core handles data transfer tasks without requiring processor intervention, thereby increasing throughput without proportionally increasing processor complexity
Solution Approach 2:
The DMA cores act as intermediary components between the processor/communication ASIC and the memory systems. These intermediaries handle the data transfer operations that would otherwise burden the processor, enabling high-speed data transfer while keeping the processor design simpler
2Productivity
If the data transfer capability between master communication ASIC and processor is improved, then the throughput is improved, but the ease of manufacture decreases due to difficulty in changing transmission path specification
Solution Approach 1:
The system uses dynamic descriptor tables that can be configured and activated based on different communication requirements. The activation unit selectively activates appropriate descriptor tables from multiple predefined tables, allowing the data transfer capability to be dynamically adjusted without changing the physical transmission path specification
Solution Approach 2:
The invention changes software parameters (descriptor table configurations, activation states) rather than hardware parameters (transmission path specification). By modifying which descriptor table is activated, the system can optimize data transfer capability for different scenarios without requiring manufacturing changes to the transmission path
3Adaptability or versatility
If multiple tasks with different priorities are executed in the arithmetic processing part, then the adaptability is improved, but the device complexity increases due to need for arbitration mechanisms
Solution Approach 1:
The DMA cores automatically arbitrate task execution based on priority information contained in the descriptor tables themselves. The system is self-sufficient in managing task priorities without requiring external arbitration control, reducing the complexity of the arbitration mechanism while maintaining multi-task processing capability
Data Source
AI summary
Provided is a control device that includes: a communication unit; one or more functional units; and a communication line connecting the communication unit and the one or the plurality of functional units. The communication unit includes: a computation processing unit in which a processor executes one or more tasks; a communication circuit which handles the transmission and reception of communication frames via the communication line; and a control circuit connected to the computation processing unit and the communication circuit. The control circuit includes: a first Direct Memory Access (DMA) core for accessing the computation processing unit; a second DMA core for accessing the communication circuit; and a controller which, in response to a trigger from the computation processing part, provides sequential commands to the first DMA core and the second DMA core in accordance with a predefined descriptor table.