DMA Engine Completion Notification via Local FIFO
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Solution Overview
Problem
Current DMA transfer completion notification methods in parallel computers introduce latency due to the need for acknowledgement messages from receiving compute nodes, which increases overhead and delays processing.
Innovation Solution
The solution involves an origin DMA engine inserting a data descriptor and a completion notification descriptor into an injection FIFO buffer, transferring the message, sending a completion notification packet to a local reception FIFO buffer, and notifying the application of transfer completion upon receiving the packet, thereby eliminating the need for acknowledgement messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DMA transfer completion notification methods are used, then transfer completion can be confirmed, but latency increases due to acknowledgement messages from receiving compute nodes
Solution Approach 1:
The patent extracts the completion notification function from the receiving compute node and places it at the sending compute node's DMA engine. The DMA engine generates and sends completion notification packets independently without waiting for acknowledgments from the receiving node, thereby eliminating the latency caused by acknowledgment messages while maintaining reliable transfer completion confirmation.
Solution Approach 2:
The patent implements preliminary action by having the DMA engine prepare and send completion notification packets in advance or concurrently with the data transfer process. The completion notification is generated based on the transfer operation parameters before the actual data transmission completes, allowing the sending node to notify the application without waiting for the receiving node's acknowledgment.
2Reliability
If acknowledgement messages are used for DMA transfer completion, then transfer reliability is ensured, but processing overhead increases
Solution Approach 1:
The patent removes the acknowledgment message mechanism from the system by implementing a push-based completion notification model. The sending DMA engine unilaterally generates and sends completion notifications to the application without requiring feedback from the receiving node, thereby eliminating the overhead associated with bidirectional acknowledgment protocols while preserving transfer reliability through deterministic completion signaling.
3Reliability
If waiting for acknowledgement messages is implemented, then transfer completion is verified, but processing speed decreases
Solution Approach 1:
The patent applies preliminary action by having the DMA engine prepare completion notification packets before the data transfer actually completes. The notification mechanism is pre-configured with transfer parameters and destination information, allowing the system to send completion signals immediately upon internal completion detection without being blocked by acknowledgment waits, thus maintaining high processing speed while verifying transfer completion reliability.
Data Source
AI summary
DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (‘FIFO’) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.