Scatter-Gather DMA Context Caching with Hot and Cold Eviction

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Solution Overview

Problem

Existing scatter-gather DMA operations suffer from inefficient context caching, leading to lengthy DMA reads from host memory and wasted bandwidth due to repeated context retrieval, especially when processing is paused or out of order.

Innovation Solution

Implementing a two-level context cache system on the network interface controller (NIC), comprising a hot context cache for imminent needs and a cold context cache for less immediate needs, to store and manage instruction context efficiently, reducing the need for repeated host memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If context is cached for subsequent instructions, then DMA processing time is reduced, but device complexity increases due to cache management requirements

Engineering Contradiction:
ImproveDMA processing timeVSAvoidcache management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The context cache is segmented into two distinct levels: a first-level context cache and a second-level context cache. This segmentation allows the system to manage different types of context information separately, reducing the complexity of managing a single large cache while still achieving the benefit of reduced DMA processing time through efficient context retrieval at the appropriate level.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If a single-level context cache is used, then device complexity is minimized, but host memory bandwidth is wasted due to repeated context reads

Engineering Contradiction:
Improvehost memory bandwidth consumptionVSAvoidcache system complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts frequently accessed context information from host memory and stores it in a dedicated first-level context cache within the DMA device. This extraction eliminates the need to repeatedly read context from host memory, reducing bandwidth consumption while the localized cache structure keeps the overall system complexity manageable.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a hierarchical dimension to the cache structure by implementing two levels of context caching. This dimensional change allows the system to optimize for both speed (first-level cache for immediate needs) and capacity (second-level cache for broader context), reducing memory bandwidth usage without requiring a single overly complex cache structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If context is cached for paused instructions, then processing resumption efficiency is improved, but cache management complexity increases

Engineering Contradiction:
Improveinstruction processing efficiencyVSAvoidcache control logic complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by pre-caching context information in the first-level context cache before instructions are fully processed or paused. When an instruction is paused, its context is already available in the cache, allowing for rapid resumption without requiring complex real-time cache management during the pause state.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12561261B1Two-level context caching and eviction for scatter-gather DMA
Publication Date: 2026.02.24 HEWLETT PACKARD ENTERPRISE DEV LP
  • US12561261B1 patent drawing
  • US12561261B1 patent drawing
  • US12561261B1 patent drawing

AI summary

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.