DMA Control Device Bypassing Processor for Multicore Data Transfer
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Solution Overview
Problem
Existing direct memory access (DMA) systems in computing units are inefficient, particularly in multicore systems, as they require processor core involvement for data transmission, leading to slow operations and limited compatibility with systems designed for single processor cores.
Innovation Solution
A direct memory access control device that connects to a bus system, reads data from a source module, determines a target address in the working memory using configuration information, and transmits data blocks directly, bypassing the need for processor core involvement, thereby enhancing data transmission efficiency and compatibility with multicore systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If processor core involvement is used for data transmission, then data transmission can be performed, but transmission speed is slow and system efficiency is reduced
Solution Approach 1:
The patent extracts the data transmission function from the processor core and assigns it to a dedicated DMA control device. The DMA control device independently handles data block transmission between source modules and working memory without requiring processor core participation, thereby eliminating the time loss associated with processor involvement in routine data transfer operations.
Solution Approach 2:
The patent introduces a DMA control device as an intermediary between source modules and working memory. This intermediary device specializes in data transmission tasks, handling address generation, data block transfer, and buffer management,ไป่ freeing the processor core from these routine operations and improving overall system efficiency.
2Adaptability or versatility
If DMA control device is designed for single processor core systems, then it works for single core systems, but it is not compatible with multicore systems
Solution Approach 1:
The patent designs the DMA control device with universal functionality to support both single-core and multicore systems. The device includes a computing unit that can determine target addresses in working memory for multiple processor cores, and can manage data transmission to different memory regions associated with different cores, making it adaptable to various system configurations without requiring redesign.
Solution Approach 2:
The patent implements dynamic configuration capabilities in the DMA control device, where the computing unit can adaptively determine target addresses based on configuration information and the specific multicore system architecture. The device can dynamically adjust its operation mode, address generation strategy, and memory access patterns to suit different core configurations, enhancing versatility without proportionally increasing complexity.
3Productivity
If processor core is involved in every data transmission operation, then data accuracy can be ensured, but system performance and productivity are reduced
Solution Approach 1:
The patent implements self-service functionality in the DMA control device, where the computing unit autonomously determines target addresses, manages data block transmission, and handles buffer operations without requiring processor core intervention. The device uses configuration information and filter criteria to automatically make decisions about data routing and memory access, ensuring data accuracy through built-in validation mechanisms while maintaining high throughput.
4Adaptability or versatility
If configuration information is stored in separate memory, then flexibility is improved, but access time and system complexity increase
Solution Approach 1:
The patent merges the configuration information storage with the DMA control device itself, integrating the configuration data into the device's internal memory or register structure. This allows the computing unit to access configuration information directly and rapidly during target address determination, eliminating the time delay associated with external memory access while maintaining the flexibility of configurable parameters for adapting to different system configurations.
Data Source
AI summary
A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, and processing circuitry configured to read out, from a source module connected to the bus system, first data of at least one information block stored at least temporarily in the source module, ascertain a target address in the working memory for the at least one information block as a function of the first data and of configuration information, and transmit the at least one information block from the source module to the target address using a direct memory access by the source module to the working memory.