DMA Controller Autonomous Address Register Transfer
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Solution Overview
Problem
Existing DMA systems require processor involvement for each data transfer operation, which can compromise security and efficiency, especially when handling sensitive data like cryptographic keys.
Innovation Solution
A DMA controller with an internal address register and transfer circuitry that allows for sequence of data transfers between multiple addresses without processor involvement, enabling secure and efficient data transfer by storing and deriving memory addresses internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor involvement is required for each data transfer operation, then data transfer can be initiated and controlled, but processing efficiency decreases and security is compromised
Solution Approach 1:
The DMA controller is configured to autonomously perform multiple data transfer operations by internally managing address registers and transfer sequences without requiring processor intervention for each operation. The controller reads data from a first memory address, automatically stores a second memory address in an address register, and continues transferring data to the specified destination, enabling self-service data transfer that improves efficiency while maintaining security through hardware-enforced address management
Solution Approach 2:
The system performs preliminary setup by storing the second memory address in the address register before the actual data transfer sequence begins. This preliminary action enables the DMA controller to execute multiple transfer operations autonomously without real-time processor involvement, resolving the contradiction by preparing necessary information in advance that allows both efficient autonomous operation and secure controlled access
2Ease of operation
If processor involvement is required for each data transfer operation, then transfer control is maintained, but processing overhead increases
Solution Approach 1:
The DMA controller autonomously manages the complete data transfer sequence including reading from source memory, storing destination addresses in internal registers, and writing to target locations without requiring processor intervention for each step. This self-service mechanism maintains transfer control through hardware-based address management while eliminating the time loss associated with processor involvement in each transfer operation
Solution Approach 2:
The data transfer operation is segmented into distinct phases: address setup phase where the second memory address is stored in the address register, and execution phase where multiple transfers occur autonomously. This segmentation allows control logic to be separated from execution, maintaining ease of operation through structured control while minimizing processing overhead by allowing bulk autonomous execution
3Adaptability or versatility
If addresses are provided by processor for each transfer, then flexibility in data transfer is maintained, but system complexity increases
Solution Approach 1:
The DMA controller is designed with universal address register functionality that can store and manage memory addresses for multiple different data transfer operations. The same address register structure handles various transfer scenarios including sequential transfers, block transfers, and different memory mappings, maintaining transfer flexibility through a unified address management mechanism while reducing the need for separate control logic for each transfer type
Data Source
AI summary
The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.