DMA Controller Buffer Segmentation for Short Payload Latency
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Solution Overview
Problem
Existing DMA technologies face challenges in reducing latency for short payloads and managing resources effectively, leading to increased latency and resource usage during data transfer in parallel computers, especially when handling variable-length packets and fixed-length packets.
Innovation Solution
The proposed solution involves a DMA controller that stores the packet header and a portion of the data in separate memories, allowing for single access to the packet buffer for short payloads and optimizing resource allocation by classifying packets based on length, thereby reducing latency and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-density buffer such as SRAM is used as a receive buffer to store a large amount of packets, then throughput of data transfer is improved, but access latency increases compared to usual receive buffers
Solution Approach 1:
The receive buffer is segmented into multiple regions: a first receive buffer region with high-speed access (using flip-flops or registers) and a second receive buffer region with high density (using SRAM). This segmentation allows the system to utilize both the speed advantage of the first region and the capacity advantage of the second region, thereby improving throughput while minimizing access latency for frequently accessed data.
2Productivity
If a receive buffer for storing a large amount of payloads is implemented to transfer payloads with long message lengths at high throughput, then throughput is improved, but resources provided in the information processing apparatus increase
Solution Approach 1:
Different regions of the receive buffer are assigned different storage media based on local requirements: the first receive buffer region uses high-speed but resource-intensive flip-flops or registers for data requiring frequent access, while the second receive buffer region uses resource-efficient SRAM for data requiring large storage capacity but less frequent access. This local quality differentiation optimizes the balance between throughput and resource consumption.
3Productivity
If different receive buffers are provided for variable-length packets and fixed-length packets, then data transfer efficiency is improved, but device complexity increases
Solution Approach 1:
The receive buffer is designed as a unified multi-functional structure that can handle both variable-length packets and fixed-length packets. The buffer includes a first receive buffer region and a second receive buffer region that can be flexibly allocated based on packet type and length requirements, eliminating the need for completely separate buffer structures for different packet types while maintaining data transfer efficiency.
Data Source
AI summary
An apparatus includes a first memory and a direct memory access (DMA) controller. The DMA controller includes a second memory to store the received packet and a third memory, and receives a packet including a header where information for DMA is registered and data to be stored in the first memory. The DMA controller acquires and stores, in the third memory, the header and a beginning portion of a given length from beginning of the data of the packet stored in the second memory. The DMA controller reads the data included in the packet from the third memory when it is determined, based on the header, that a data length of the data included in the packet is less than or equal to the given length, and performs storage of the read data by DMA in the first memory.