DMA Controller Buffering for Multiprocessor Idle Time Reduction
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Solution Overview
Problem
Existing information processing systems face inefficiencies due to the lack of coordinated control over graphic processors, leading to idle time in both main and graphic processors, which hampers high-performance processing.
Innovation Solution
The implementation of a system with a main processor exercising centralized control, a graphic processor, and multiple buffers in the graphic memory, utilizing DMA controllers to manage data transfer and synchronization commands like SYNC, KICK, and NOTIFY, allowing for parallel processing and reduced idle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the main processor operates at high speed with multiple tasks, then processing throughput is improved, but the graphic processor cannot keep up causing idle time and reduced efficiency
Solution Approach 1:
The patent segments the data transfer process by introducing multiple buffers (first buffer, second buffer, third buffer) in the graphic memory. This allows the main processor and graphic processor to operate independently on different data segments simultaneously, eliminating the idle time caused by sequential data transfer while maintaining high processing throughput.
Solution Approach 2:
The patent implements preliminary action by pre-loading data into buffers before the graphic processor needs it. The main processor can transfer data to buffers in advance using DMA controllers, so when the graphic processor is ready to process, the data is already available, eliminating waiting time and ensuring continuous high-speed operation.
2Device complexity
If data is transferred sequentially from main memory to graphic memory, then memory access is simplified, but processing speed is reduced due to idle waiting time
Solution Approach 1:
The patent divides the data transfer process into multiple parallel channels by introducing multiple buffers. Different DMA controllers can transfer data to different buffers simultaneously, transforming sequential memory access into parallel operations, thereby increasing data transfer speed while maintaining relatively simple memory access structure.
Solution Approach 2:
The patent ensures continuous useful action by implementing a pipeline architecture where data transfer and graphic processing occur simultaneously and continuously. While one buffer is being processed by the graphic processor, another buffer is being filled by the DMA controller, eliminating idle waiting time and maximizing processing speed.
3Adaptability or versatility
If the graphic processor operates independently without coordinated control, then processing autonomy is improved, but system efficiency deteriorates due to lack of synchronization
Solution Approach 1:
The patent implements feedback mechanisms through synchronization commands (SYNC, KICK, NOTIFY) that allow the graphic processor to communicate its status and needs to the main processor. This feedback enables coordinated control while maintaining processor autonomy, ensuring that data transfer and processing are synchronized for optimal system efficiency.
Solution Approach 2:
The patent introduces synchronization commands and buffer management mechanisms as intermediaries between the main processor and graphic processor. These intermediaries facilitate coordinated control by managing data flow and synchronization without requiring direct processor-to-processor communication, thus maintaining autonomy while improving system efficiency.
Data Source
AI summary
The invention is provided to improve the information processing efficiency of a multiprocessor system. An information processing apparatus 1000 comprises a main processor 200 for exercising centralized control on the entire apparatus, a graphic processor 100 for performing image processing operations, and a main memory 50. The information processing apparatus 1000 also comprises a DMA controller 28 which controls m (m is an integer, m>1) pieces of data transfer simultaneously, a main memory 50 for data intended for the particular processing is expanded first, and a group of n (n is an integer, n>m) buffers 12 for storing data when the data is transferred from the main memory 50. When a plurality of data transfers are performed simultaneously, a first buffer out of the group of buffers 12 is set as the destination of one of the data transfers, and a second buffer is set as the destination of another data transfer.